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| 型号： | T9000 |
| 厂商： | Lineage Power |
| 英文描述： | ISDN Network Termination Node (NTN) Device(ISDN网络终端节点器件) |
| 中文描述： | ISDN网络终端节点（新界西）设备（ISDN网网络终端节点器件） |
| 文件页数： | 3/126页 |
| 文件大小： | 1523K |
| 代理商： | T9000 |
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Advance Data Sheet
April 2000
Lucent Technologies Inc.
3
ISDN Network Termination Node (NTN) Device
T9000
Table of Contents
(continued)
Tables
Page
Table 1. S/T-Interface Pins (6) ..................................8
Table 2. U-Interface Pins (7) .....................................8
Table 3. GCI+ Pins (5) ...............................................9
Table 4. GPIO Pins (24) ..........................................10
Table 5. 80C32 External Access Pins (27) ...............11
Table 6. Comparators (6) ........................................13
Table 7. JTAG Pins (4) ............................................13
Table 8. Miscellaneous Pins (2) ..............................14
Table 9. Oscillator Pins (2) ......................................14
Table 10. Power and Ground Pins ..........................14
Table 11. Control Register Memory Space ...............15
Table 12. GIR0: Global Interrupt Register 0
(0x00) ....................................................................18
Table 13. GIR1: Global Interrupt Register 1
(0x01) ....................................................................19
Table 14. GIE: Global Interrupt Enable Register
(0x02) .....................................................................20
Table 15. UPCK: Microcontroller Clock Control
Register (0x03) .....................................................21
Table 16. WDT: Microcontroller Watchdog Timer
Control (0x04) .......................................................22
Table 17. Port Direction Registers ...........................24
Table 18. Standard 80C32 RCLK/TCLK Options ....25
Table 19. Lucent 80C32 RCLK/TCLK Options ........25
Table 20. External Program Memory
Characteristics........................................................26
Table 21. AUTOEOC = 1 Messages
(Data/Messages = 1) That Initiate Actions ............31
Table 22. DFCF: DFAC Configuration Register
(0x05) ....................................................................33
Table 23. DFR: Data Flow Register
(0x06) ....................................................................34
Table 24. UCR0: U-Interface Control Register #0
(0x07) ....................................................................35
Table 25. UCR1: U-Interface Control Register #1
(0x08) ....................................................................36
Table 26. USR0: U-Interface Status Register #0
(0x09) ....................................................................37
Table 27. USR1: U-Interface Status Register #1
(0x0A) ...................................................................37
Table 28. ECR0: EOC Control Register 0—Command
and Address (0x0B) ..............................................38
Table 29. ECR1: EOC Control Register 1—Message
(0x0C) ...................................................................39
Table 30. ESR0: EOC Status Register 0—Command
and Address (0x0D) ..............................................39
Table 31. ESR1: EOC Status Register 1—Message
(0x0E) ...................................................................39
Table 32. SCR0: S-Interface Control Register #0
(0x0F) ....................................................................40
Table 33. SCR1: S-Interface Control Register #1
(0x10) ....................................................................41
Tables
Page
Table 34. SSR: S-Interface Status Register
(0x11) ................................................................... 42
Table 35. MFR0: Multiframe Register, Q-Chan-
nel Data (0x12) .................................................... 43
Table 36. MFR1: Multiframe Register, S-Sub-
channel Data (0x13) ............................................. 43
Table 37. UIR: U-Interface Interrupt Register
(0x14) ................................................................... 44
Table 38. UIE: U-Interface Interrupt Enable
(0x15) .................................................................... 45
Table 39. SIR: S-Interface Interrupt Register
(0x16) ................................................................... 46
Table 40. SIE: S-Interface Interrupt Enable Register
(0x17) .................................................................... 46
Table 41. DOCR: Device Operation Control
Register (0x50) ...................................................... 47
Table 42. B1UP: B1-Channel Upstream Data
from GCI to U-interface (0x51)............................... 47
Table 43. B2UP: B2-Channel Upstream Data
from GCI to U-interface (0x52)............................... 48
Table 44. B1DN: B1-Channel Downstream Data
from
U-Interface
to GCI (0x53) .............................. 48
Table 45. B2DN: B2-Channel Downstream Data
from
U-Interface
to GCI (0x54) .............................. 48
Table 46. Reserved 1: Reserved Register for
Internal Use (0x55) ................................................ 49
Table 47. Reserved 2: Reserved Register for
Internal Use (0x56) ................................................ 49
Table 48. Reserved 3: Reserved Register for
Internal Use (0x57) ................................................ 49
Table 49. Reserved 4: Reserved Register for
Internal Use (0x58) ................................................ 50
Table 50. Reserved 5: Reserved Register for
Internal Use (0x59) ................................................ 50
Table 51. Reserved 6: Reserved Register for
Internal Use (0x5A)................................................ 50
Table 52. Reserved 7: Reserved Register for
Internal Use (0x5B)................................................ 50
Table 53. Reserved 8: Reserved Register for
Internal Use (0x5C)................................................ 51
Table 54. Reserved 9: Reserved Register for
Internal Use (0x5D)................................................ 51
Table 55. HTCF: HDLC Transmitter Configuration
Register (0x18) .................................................... 58
Table 56. HRCF: HDLC Receiver Configuration
Register (0x19) .................................................... 59
Table 57. HTTH: HDLC Transmit FIFO Threshold
(0x1A) .................................................................. 60
Table 58. HRTH: HDLC Receive FIFO Threshold
(0x1B) .................................................................. 60
Table 59. HTSA: HDLC Transmit FIFO Space
Available (0x1C) ................................................... 61
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