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参数资料
| 型号： | T9000 |
| 厂商： | Lineage Power |
| 英文描述： | ISDN Network Termination Node (NTN) Device(ISDN网络终端节点器件) |
| 中文描述： | ISDN网络终端节点（新界西）设备（ISDN网网络终端节点器件） |
| 文件页数： | 58/126页 |
| 文件大小： | 1523K |
| 代理商： | T9000 |
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58
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.5 HDLC Register Set
Table 55. HTCF: HDLC Transmitter Configuration Register (0x18)
Reg
HTCF
RESET
R/W
R/W
Default
Bit 7
FCNT2
0
Bit 6
FCNT1
0
Bit 5
FCNT0
0
Bit 4
IDL
1
Bit 3
TXMODE ABRT_RQ MANCRC
0
0
Bit 2
Bit 1
Bit 0
TX_INIT
0
0
Bit #
7—5
Symbol
FCNT[2:0]
Name/Description
Interframe Fill Count
. Sets the number of fill bytes to be transmitted between each
HDLC frame. The number of fill bytes inserted between the closing flag of one frame and
the opening flag of another is FCNT[2:0]
1, except for the case of FCNT[2:0] = 0, which
causes sharing of the closing flag of one frame with the opening flag of the next.
000: Back-to-back frames (closing/opening flag is shared).
001: No fill bytes are inserted.
. . .
111: Insert 6 fill bytes.
Back-to-back frames can only occur if the priority mechanism is disabled by setting
DFR[FORCE_D] = 1. See DFR[FORCE_D] description.
Idle/Interframe Fill Value.
Sets the value of the transmitter’s idle and interframe fill
bytes.
4
IDL
0: 01111110 (flags)
1: 11111111 (idles)
Flags can only be used as idle or interframe fill bytes if the priority mechanism is disabled
by setting DFR[FORCE_D] = 1. See DFR[FORCE_D] description.
Transmitter Mode
. Determines whether the transmitter is in standard HDLC mode or
transparent mode. The transmitter must be reinitialized after changing this bit.
3
TXMODE
0: Standard HDLC mode.
1: Transparent mode.
HDLC Transmitter Abort Request.
When this signal is written to 1, the frame
currently being transmitted is aborted and the transmit FIFO will be flushed. This bit
automatically returns to 0 once the abort sequence has been set.
HDLC Transmitter Manual/Auto CRC Insertion
. Controls whether the transmit FCS
(CRC) will be inserted automatically by the HDLC controller or whether it must be manu-
ally loaded into the transmit FIFO. The transmitter must be reinitialized after changing
this bit.
2
ABRT_RQ
1
MANCRC
0: Auto insertion.
1: Manual insertion.
HDLC Transmitter Initialize
. Writing this bit to 1 will cause initialization of the HDLC
transmitter. On powerup, the HDLC transmitter is initialized automatically. After powerup,
whenever the MANCRC or TXMODE configuration bits are changed, this bit needs to be
set to reinitialize the HDLC transmitter. Prior to programming any of the transmitter regis-
ters, this bit must be written to 1. The microcontroller must then poll this bit and wait until
it returns to 0 (signaling that transmitter initialization is complete) before programming
any of the other transmitter registers.
0
TX_INIT
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