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参数资料
| 型号： | TC58NS256DC |
| 厂商： | Toshiba Corporation |
| 英文描述： | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ?8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM) |
| 中文描述： | 马鞍山暂定东芝数字集成电路硅栅CMOS 256兆位（32M的？8位）的CMOS NAND型E2PROM的（32兆字节SmartMediaTM） |
| 文件页数： | 15/33页 |
| 文件大小： | 709K |
| 代理商： | TC58NS256DC |
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TC58NS256DC
2000-08-27 15/33
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device
pin-outs are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the
operation mode command into the internal command register.
The command is latched into the command register from the I/O
port on the rising edge of the WE signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either address
information or input data into the internal address/data register.
Address information is latched on the rising edge of WE if ALE
is High. Input data is latched if ALE is Low.
Chip Enable:
The device goes into a low-power Standby mode when CE
goes High during a Read operation. The CE signal is ignored
when device is in Busy state (
RY
Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy
state to ensure that memory array data is correctly transferred to the data register.
BY
/
=
L), such as during a Program or Erase operation, and will not enter
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available t
REA
after the falling edge of RE .
The internal column address counter is also incremented (Address
=
Address
+
1) on this falling edge.
I/O Port: I/O1~I/O8
The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY
The
Busy state (
(
BY
/
RY
BY
/
RY
output signal is used to indicate the operating condition of the device. The
BY
/
RY
=
L) during the Program, Erase and Read operations and will return to Ready state
=
H) after completion of the operation. The output buffer for this signal is an open drain.
BY
/
RY
signal is in
Low Voltage Detect: LVD
The LVD signal is used to detect the power supply voltage level.
TC58NS256DC
V
SS
CLE ALE
I/O1 I/O2 I/O3 I/O4 V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
BY
/
RY
V
CC
GND LVD I/O8 I/O7 I/O6 I/O5 V
CC
22
21
20
19
18
17
16
15
14
13
12
WE WP
CE
RE
Figure 1. Pinout
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