参数资料
型号: TC58NS256DC
厂商: Toshiba Corporation
英文描述: TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ?8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)
中文描述: 马鞍山暂定东芝数字集成电路硅栅CMOS 256兆位(32M的?8位)的CMOS NAND型E2PROM的(32兆字节SmartMediaTM)
文件页数: 16/33页
文件大小: 709K
代理商: TC58NS256DC
TC58NS256DC
2000-08-27 16/33
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
A page consists of 528 bytes in which 512 bytes are
used for main memory storage and 16 bytes are for
redundancy or for other uses.
1 page
=
528 bytes
1 block
=
528 bytes
×
32 pages
=
(16K
+
512) bytes
Capacity
=
528 bytes
×
32 pages
×
2048 blocks
An address is read in via the I/O port over three
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
First cycle
A7
A6
A5
A4
A3
A2
A1
A0
Second cycle
A16
A15
A14
A13
A12
A11
A10
A9
Third cycle
A24
A23
A22
A21
A20
A19
A18
A17
A0~A7:
A9~A24: Page address
A14~A24: Block address
A9~A13: NAND address in block
Column address
*
: A8 is automatically set to Low or High by a 00H command or a 01H command.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE, CE, WE, RE and WP signals, as shown in Table 2.
Table 2. Logic table
CLE
ALE
CE
WE
RE
WP
Command Input
H
L
L
H
*
Data Input
L
L
L
H
*
Address Input
L
H
L
H
*
Serial Data Output
L
L
L
H
*
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
Program, Erase Inhibit
*
*
*
*
*
L
H: V
IH
, L: V
IL
,
*
: V
IH
or V
IL
32 pages
1 block
16
512
I/O1
I/O8
8I/O
528
65536 pages
2048 blocks
=
Figure 2. Schematic Cell Layout
=
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