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参数资料
| 型号： | TC58NS256DC |
| 厂商： | Toshiba Corporation |
| 英文描述： | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ?8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM) |
| 中文描述： | 马鞍山暂定东芝数字集成电路硅栅CMOS 256兆位（32M的？8位）的CMOS NAND型E2PROM的（32兆字节SmartMediaTM） |
| 文件页数： | 21/33页 |
| 文件大小： | 709K |
| 代理商： | TC58NS256DC |
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TC58NS256DC
2000-08-27 21/33
Auto Page Program
The device carries out an Automatic Page Program operation when it receives a 10H Program command after
the address and data have been input. The sequence of command, address and data input is shown below. (Refer
to the detailed timing chart.)
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command D0H which
follows the Erase Setup command 60H. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
80
10
Data input
0~527
70
I/O
Address
input
Data input
command
Program
command
Status Read
command
Fail
BY
/
RY
BY
/
RY
completion of the operation.
automatically returns to Ready after
Figure 7. Auto Page Program operation
The data is transferred (programmed) from the register to the selected
page on the rising edge of WE following input of the 10H command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the
device until success is achieved or until the maximum loop number set in
the device is reached.
Data input
Selected
page
Reading & verification
Program
Pass
I/O
Fail
BY
/
RY
60
D0
70
Block address
input: 2 cycles
Status Read
command
Busy
Erase Start
command
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| TC58NVG0S3AFT05 | 制造商:TOSHIBA 制造商全称:Toshiba Semiconductor 功能描述:1 GBIT (128M 】 8 BITS) CMOS NAND EEPROM |
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