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| 型号： | TC58NS256DC |
| 厂商： | Toshiba Corporation |
| 英文描述： | TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ?8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM) |
| 中文描述： | 马鞍山暂定东芝数字集成电路硅栅CMOS 256兆位（32M的？8位）的CMOS NAND型E2PROM的（32兆字节SmartMediaTM） |
| 文件页数： | 30/33页 |
| 文件大小： | 709K |
| 代理商： | TC58NS256DC |
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TC58NS256DC
2000-08-27 30/33
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 10 segments. Each segment can be programmed individually as follows:
(13)
Note regarding the RE signal
The internal column address counter is incremented synchronously with the RE clock in Read mode.
Therefore, once the device has been set to Read mode by a 00H, 01H or 50H command, the internal column
address counter is incremented by the RE clock independently of the address input timing. If the RE
clock input pulses start before the address input, and the pointer reaches the last column address, an
internal read operation (array
→
register) will occur and the device will enter Busy state. (Refer to Figure
25.)
Hence the RE clock input must start after the address input.
Figure 25.
Address input
WE
I/O
BY
/
RY
RE
00H/01H/50H
Data Pattern 10
Data Pattern 1
All 1s
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be 1
(i.e. the inputs for all page bytes outside the segment which is to be programmed should
be set to all 1).
First programming
Second programming
Tenth programming
Result
Data Pattern 1
Data Pattern 10
Data Pattern 2
All 1s
All 1s
Data Pattern 2
All 1s
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