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参数资料
| 型号： | TRC105 |
| 厂商： | RFM |
| 文件页数： | 12/67页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 300MHZ-510MHZ 32TQFN |
| 标准包装： | 1 |
| 频率： | 300MHz ~ 510MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 13dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1159-6 |
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The TRC105 transmitter and receiver sections support three data handling modes of operation:
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Continuous mode: each bit transmitted or received is accessed directly at the DATA input/output pin.
Buffered mode: a 64-byte FIFO is used to store each data byte transmitted or received. This data is writ-
ten to and read from the FIFO through the SPI bus.
Packet handling mode: in addition to using the FIFO, this data mode builds the complete packet in
transmit mode and extracts the useful data from the packet in receive mode. The packet includes a pre-
amble, a start pattern (network address), an optional node address and length byte and the data. Packet
data mode can also be configured to perform additional operations like CRC error detection and DC-
balanced Manchester encoding or data scrambling.
The buffered and packet handling modes allow the host microcontroller overhead to be significantly reduced.
The DATA pin is bidirectional and is used in both transmit and receive modes. In receive mode, DATA represents
the demodulated received data. In transmit mode, input data is applied to this pin.
The working length of the FIFO can set to 16, 32, 48 or 64 bytes through the MCFG0C_FIFO_depth[7..6] regis-
ter. In the discussions below describing the FIFO behavior, the explanations are given with an assumption of 64
bytes, but the principle is the same for the four possible FIFO sizes.
The status of the FIFO can be monitored via interrupts which are described in Section 3.7. In addition to the
straightforward nFIFOEMPY and FIFOFULL interrupts, additional configurable interrupts Fifo_Int_Tx and
Fifo_Int_Rx are also available.
A low-to-high transition occurs on Fifo_Int_Rx when the number of bytes in the FIFO is greater than or equal to
the threshold set by MCFG0C_FIFO_thresh[5..0] (number of bytes ≥ FIFO_thresh).
A low-to-high transition occurs on Fifo_Int_Tx when the number of bytes in the FIFO is less than or equal to the
threshold set by MCFG0C_FIFO_thresh[5..0] (number of bytes ≤ FIFO_thresh).
3.1 Receiving in Continuous Data Mode
The receiver operates in Continuous data mode when the MCFG01_Mode[7..6] bits are set to 00. In this mode,
the receiver has two output signals indicating recovered clock, DCLK and recovered NRZ bit DATA. DCLK is con-
nected to output pin IRQ1 and DATA is connected to pin DATA configured in output mode. The data and clock
recovery controls the recovered clock signal, DCLK. Data and clock recovery is enabled by RXCFG12_DCLK_
Dis[6] to 0 (default value). The clock recovered from the incoming data stream appears at DCLK. When data and
clock recovery is disabled, the DCLK output is held low and the raw demodulator output appears at DATA. The
function of data and clock recovery is to remove glitches from the data stream and to provide a synchronous clock
at DCLK. The output DATA is valid at the rising edge of DCLK as shown in Figure 8.
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 12 of 67
TRC105 - 05/29/13
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