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参数资料
| 型号： | TRC105 |
| 厂商： | RFM |
| 文件页数： | 21/67页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 300MHZ-510MHZ 32TQFN |
| 标准包装： | 1 |
| 频率： | 300MHz ~ 510MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 13dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1159-6 |
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Figure 15
In extended variable length packet mode, the length of the rest of the payload is given by the first byte written to
the FIFO. The length byte itself is not included in this count. There are a number of ways to use the extended var-
iable length packet capability. The most common way is outlined below:
1. Set PKTCFG1C_Pkt_len[6..0] to a value between 65 (0x41) and 127 (0x7F). This sets the maximum allowed
payload in extended packet mode. Any received packet having a value in the length byte greater than this maxi-
mum is discarded.
2. Set PKTCFG1E_Pkt_mode[7 ] to 1 for variable length packet mode operation. Set the PKTCFG1E_ Pre-
amb_len[6..5] bits to 10 or 11 for a 3 or 4 byte preamble. Set the PKTCFG1E_CRC_En[3] bit to 1 to enable CRC
processing. Set the PKTCFG1E_Pkt_ADDRS_cmp[2..1] bits as required. Clear the PKTCFG1E_ CRC_stat[0]
bit by writing a 1 to it.
3. Set MCFG0C_FIFO_depth[7..6] bits to 11 for a 64 byte FIFO length.
4. Set the MCFG0C_FIFO_thresh[5..0] to approximately 31(0x1F). This sets the threshold to 32, near the mid
point of the FIFO. Provided the host microcontroller is relatively fast (usual case), this setting can be used for
monitoring the FIFO in both transmit and receive. If the host microcontroller is relatively slow, set the threshold to
a value lower than 31 for receive, and higher than 31 for transmit.
5. Set the IRQCFG0D_RX_IRQ1[5..4] bits to 11. This maps FIFO_Int_Rx interrupt to IRQ1, which trips when the
number of received bytes in the FIFO is equal to or greater than the value in MCFG05_FIFO_thresh. IRQ1 will
then signal received bytes must be retrieved. If received bytes are not retrieved before the FIFO completely fills,
data will be lost.
6. Set the IRQCFG0D_TX_IRQ0[3] bit to 0. This causes a transmission to start when the number of transmit
bytes in the FIFO is equal to or greater than the value in MCFG0C_FIFO_thresh. Also, the FIFO_Int_Tx interrupt
is mapped to IRQ0 in transmit mode, and is set when the number of bytes in the FIFO is equal to or less than the
value in MCFG0C_FIFO_thresh. IRQ0 will then signal more bytes can be added to the FIFO. If more message
bytes are not added in time, the transmission will cease prematurely and data will be lost. Likewise, if more bytes
are sent to the FIFO than it has room for, data will be lost.
7. When receiving an extended variable length packet, monitor IRQ1. When IRQ1 trips, clock out some of the re-
ceived bytes from the FIFO (leave at least one byte in the FIFO). Repeat the partial packet retrieval each time
IRQ1 triggers. The first byte received is the number of message bytes, and can be used to tell when the last mes-
sage byte has been retrieved. When it is determined that the remaining message bytes will not overflow the FIFO,
the IRQCFG0D_RX_IRQ1[5..4] bits can be set to 00, which maps CRC_OK to IRQ1. After the CRC is checked,
the final bytes can be read from the FIFO and the IRQCFG0D_RX_IRQ1[5..4 ] bits can be reset to 11 to track
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TRC105 - 05/29/13
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