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参数资料
| 型号： | TRC105 |
| 厂商： | RFM |
| 文件页数： | 19/67页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 300MHZ-510MHZ 32TQFN |
| 标准包装： | 1 |
| 频率： | 300MHz ~ 510MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 13dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1159-6 |
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Table 12
IRQCFG0D_TX_IRQ1
0
1
0
1
0
1
Data Mode
Continuous
Continuous
Buffered
Buffered
Packet
Packet
IRQ1
Output
Output
Output
Output
Output
Output
IRQ0 Interrupt Source
DCLK
DCLK
FIFOFULL
TX_Stop
FIFOFULL
TX_Stop
Table 13
3.8 Buffered Clock Output
The buffered clock output is a signal derived from F XTAL . It can be used as a reference clock for the host microcon-
troller and is output on the CLKOUT pin. The OSCFG1B_Clkout_En[7] bit controls the CLKOUT pin. When this
bit is set to 1, CLKOUT is enabled, otherwise it is disabled. The output frequency of CLKOUT is defined by the
value of the OSCFG1B_Clk_freq[6..2] parameter which gives the frequency divider ratio applied to F XTAL . Refer
to Table 42 for programming details. Note: CLKOUT is disabled when the TRC105 is in sleep mode. If sleep
mode is used, the host microcontroller must have provisions to run from its own clock source.
3.9 Packet Data Mode
The TRC105 provides optional on-chip RX and TX packet handling features. These features ease the develop-
ment of packet oriented wireless communication protocols and free the MCU resources for other tasks. The op-
tions include enabling protocols based on fixed and variable packet lengths, data scrambling, CRC checksum cal-
culations and received packet filtering. All the programmable parameters of the Packet data mode are accessible
through the PKTCFG configuration registers of the device. The Packet data mode is enabled when the register bit
MCFG01_Mode[7..6 ] is set to 10 or 11.
The packet handler supports three types of packet formats: fixed length packets, variable length packets, and ex-
tended variable length packets. The PKTCFG1E_Pkt_mode[7] bit selects either the fixed or the variable length
packet formats.
3.9.1 Fixed Length Packet Mode
The fixed length packet mode is selected by setting the PKTCFG1E_Pkt_mode[7] bit to 0. In this mode the
length of the packet is set by the PKTCFG1C_Pkt_len[6..0] register up to the size of the FIFO which has been
selected.
The length stored in this register is the length of the payload which includes the message data bytes and optional
address byte. The fixed length packet format shown in Figure 13 is made up of the following fields:
1. Preamble
2. Start pattern (network address)
3. Node address byte (optional)
4. Data bytes
5. Two-byte CRC checksum (optional)
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 19 of 67
TRC105 - 05/29/13
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