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参数资料
| 型号： | TRC105 |
| 厂商： | RFM |
| 文件页数： | 55/67页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 300MHZ-510MHZ 32TQFN |
| 标准包装： | 1 |
| 频率： | 300MHz ~ 510MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 13dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1159-6 |
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Configuration
MCFG00 bits 4..2
P
S
R
315 MHz
000
41
1
143
434 MHz
011
76
13
191
447 MHz
100
58
46
143
Table 73
The RF channel frequency for OOK transmit is:
F RXRF = (14.4*(75*(P + 1) + S)/(R + 1)) - F IF2 , with P, S in the range 0 to 255, R in the range of 64 to 169
Where F RXRF and the OOK 2
nd
IF frequency F IF2 are in MHz, and P, S, and R are divider integers where S must be
less than (P+1), and R has a value in the range of 64 to 169. An F IF2 value of 0.1 MHz is normally used. The val-
ues of P, S and R for OOK transmit operation on several common frequencies are given in Table 74 for a
0.1 MHz F IF2 . Software for determining P, S and R values is provided with the TRC105 development kit.
Configuration
MCFG00 bits 4..2
P
S
R
315 MHz
000
41
1
143
434 MHz
011
76
13
191
447 MHz
100
58
46
143
Table 74
6.6 TRC105 Data Mode Selection and Configuration
The TRC105 supports three data modes: Continuous, Buffered and Packet. Continuous data mode provides the
most formatting flexibility, but places the heaviest demand on host microcontroller resources and requires the
most custom firmware development. In contrast, the Packet data mode unloads the host processor and the appli-
cation firmware from handing tasks such as DC-balanced data encoding, packet frame assembly and disassem-
bly, error detection, packet filtering and FIFO buffering. The trade-off for Packet data mode is limited flexibility in
data formatting parameters such as packet frame design. Buffered data mode falls between Packet and Continu-
ous data mode capabilities, providing FIFO buffering, but allowing considerable flexibility in the design of the
packet frame.
Packet data mode is generally preferred as it supports the fastest application development time and requires the
smallest and least expensive host microcontroller. Buffered data mode covers applications that require a specific
packet frame design to support features such as multi-hop routing. Continuous data mode is reserved for special-
ized requirements, such as compatibility with a legacy product.
MCFG01 bits 7..6 select the data mode. A 00 bit pattern selects Continuous data mode. A 01 bit pattern selects
Buffered data mode. Bit patterns 10 or 11 select Packet data mode. The TRC105 configuration details for each
data mode are discussed below.
6.6.1 Continuous Data Mode
In Continuous data mode operation, transmitted data streams are applied to DATA Pin 20, and received data
streams are output on Pin 20. IRQ1 Pin 22 is usually configured to supply a clock signal to the host micro-
controller to pace the transmitted and received data steams. The clock signal is generated at the configured bit
rate. When transmitting, bits are clocked into Pin 20 on the low-to-high clock transitions at Pin 22.
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 55 of 67
TRC105 - 05/29/13
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