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参数资料
| 型号： | TRC105 |
| 厂商： | RFM |
| 文件页数： | 16/67页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 300MHZ-510MHZ 32TQFN |
| 标准包装： | 1 |
| 频率： | 300MHz ~ 510MHz |
| 数据传输率 - 最大： | 200kbps |
| 调制或协议： | FSK，OOK |
| 应用： | 通用 |
| 功率 - 输出： | 13dBm |
| 灵敏度： | -112dBm |
| 电源电压： | 2.1 V ~ 3.6 V |
| 电流 - 接收： | 3mA |
| 电流 - 传输： | 30mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-TQFN |
| 包装： | 标准包装 |
| 产品目录页面： | 583 (CN2011-ZH PDF) |
| 其它名称： | 583-1159-6 |
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Figure 11
When the TRC105 is in receive mode and MCFG01_Mode [7..6 ] bits are set to 01, all of the blocks described
above are enabled. In a normal communication frame the data stream is comprised of a 24-bit preamble, a start
pattern and data. Upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the
preamble and start pattern, and stores the data in the FIFO for retrieval by the host microcontroller. This automat-
ed data extraction reduces the loading on the host microcontroller.
The IRQCFG0E_Start_Fill[7] bit determines how the FIFO is filled. If IRQCFG0E_Start_Fill[7] is set to 0, data
only fills the FIFO when a start pattern is detected. Received data bits are shifted into the pattern recognition
block which continuously compares the received data with the contents of the SYNCFG registers. If a match oc-
curs, the start pattern detect block output is set for one bit period and the IRQCFG0E_Start_Det[6] bit is also set.
This internal signal can be mapped to the IRQ0 output using interrupt signal mapping. Once a pattern match has
occurred, the start pattern detect block will remain inactive until the IRQCFG0E_Start_Det[6] bit is reset.
If IRQCFG0E_Start_Fill[7] is set to 1, FIFO filling is initiated by asserting IRQCFG0E_Start_Det[6] . Once 64
bytes have been written to the FIFO the IRQCFG0D_FIFOFULL[1] signal is set. Data should then be read out. If
no action is taken, the FIFO will overflow and subsequent data will be lost. If this occurs the IRQCFG0E_FIFO_
OVR[4] bit is set to 1. The IRQCFG0D_FIFOFULL[1] signal can be mapped to pin IRQ1 as an interrupt for a mi-
crocontroller if IRQCFG0D_RX_IRQ1[5..4] is set to 01. To recover from an overflow, a 1 must be written to
IRQCFG0D_ FIFO_OVR[4] . This clears the contents of the FIFO, resets all FIFO status flags and re-initiates pat-
tern detection. Pattern detection can also be re-initiated during a FIFO filling sequence by writing a 1 to
IRQCFG0E_Start_Det[6] .
The details of the FIFO filling process are shown in Figure 12. As the first byte is written into the FIFO, signal
IRQCFG0D_nFIFOEMPY[0] is set indicating at least one byte is present. The host microcontroller can then read
the contents of the FIFO through the SPI interface. When all data is read from the FIFO, IRQCFG0D_
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TRC105 - 05/29/13
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