参数资料
型号: WJLXT972ALC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 14/97页
文件大小: 1281K
代理商: WJLXT972ALC.A4
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Datasheet
21
Document Number: 249186-004
Revision Date: 25-Oct-2005
Table 9 lists signal descriptions of the LXT972A Transceiver power, ground, and no-connect pins.
Table 10 lists signal descriptions of the LXT972A Transceiver Joint Test Action Group (JTAG)
pins.
Note:
If a JTAG port is not used, these pins do not need to be terminated.
Table 9.
Intel LXT972A Transceiver Power, Ground, No-Connect Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
51
VCCD
Digital Power.
Requires a 3.3 V power supply.
7, 11, 13,
14, 15,
16, 18,
25, 26,
32, 34,
35, 41,
50, 61
GND
Ground.
8, 40
VCCIO
MII Power.
Requires either a 3.3 V or a 2.5 V supply. Must be supplied
from the same source used to power the MAC on the other
side of the MII.
For the LXT972A Transceiver, VCCIO is 3.3 V.
21, 22
VCCA
Analog Power.
Requires a 3.3 V power supply.
9, 10, 44
NC
-
No Connection.
These pins are not used and should not be terminated.
Table 10. Intel
LXT972A Transceiver JTAG Test Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
27
TDI
I
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
28
TDO
O
Test Data Output.
Test data driven with respect to the falling edge of TCK.
29
TMS
I
Test Mode Select.
30
TCK
I
Test Clock.
Clock input for boundary scan.
31
TRST_L
I
Test Reset.
This active-low test reset input is sourced by ATE.
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