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| 型号： | WJLXT972ALC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 83/97页 |
| 文件大小： | 1281K |
| 代理商： | WJLXT972ALC.A4 |
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Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
84
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
Table 47 lists auto-negotiation expansion bits.
Table 47. Auto-Negotiation Expansion - Address 6, Hex 6
Bit
Name
Description
Type 1
Default
6.15:6
Reserved
Ignore when read.
RO
0
6.5
Base Page
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is used only if Register bit
16.1 (that is, Alternate NP feature) is set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
RO/LH
0
6.4
Parallel
Detection Fault
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
RO/LH
0
6.3
Link Partner
Next Page Able
0 = Link partner is not next page able.
1 = Link partner is next page able.
RO
0
6.2
Next Page Able
0 = Local device is not next page able.
1 = Local device is next page able.
RO
1
6.1
Page Received
This bit is cleared on Read. If Register bit 16.1 is set,
the Page Received bit is also cleared when either
mr_page_rx = false or transmit_disable = true.
1 = Indicates a new page is received and the received
code word is loaded into Register 5 (Base Pages)
or Register 8 (Next Pages) as specified in Clause
28 of IEEE 802.3.
RO/LH
0
6.0
Link Partner A/N
Able
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
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| WJLXT972MLCA4 | 制造商:Cortina Systems Inc 功能描述: |
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