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| 型号： | WJLXT972ALC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 20/97页 |
| 文件大小： | 1281K |
| 代理商： | WJLXT972ALC.A4 |
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Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Datasheet
27
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.2.2
MII Data Interface
The LXT972A Transceiver supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes data
between the LXT972A Transceiver and a Media Access Controller (MAC). Separate parallel buses
are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The
speed is set automatically, once the operating conditions of the network link have been determined.
For details, see Section 5.6, “MII Operation” on page 38.
Increased MII Drive Strength. A higher Media Independent Interface (MII) drive strength may
be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive
loads, through multiple vias, or through a connector. The MII drive strength in the LXT972A
Transceiver can be increased by setting Register bit 26.11 through software control. Setting
Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV,
RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
5.2.3
Configuration Management Interface
The LXT972A Transceiver provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
5.2.3.1
MDIO Management Interface
MDIO management interface topics include the following:
The LXT972A Transceiver supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972A Transceiver. The MDIO interface consists of a
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972A Transceiver also supports additional registers for expanded functionality. The LXT972A
Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific register bits
are referenced using an “X.Y” notation, where X is the register number (0-31) and Y is the bit
number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
5.2.3.1.1
MDIO Addressing for Intel LXT972A Transceiver
The MDIO addressing protocol allows a controller to communicate with multiple LXT972A
Transceivers. Pin ADDR0 determines the PHY device address that is selected as follows.
Connect pin ADDR0 low to get PHY address 0.
Connect pin ADDR0 high to get PHY address 1.
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