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| 型号： | WJLXT972ALC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 36/97页 |
| 文件大小： | 1281K |
| 代理商： | WJLXT972ALC.A4 |
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Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Datasheet
41
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
CRS is always generated when the LXT972A Transceiver receives a packet from the line.
CRS is also generated when the LXT972A Transceiver is in half-duplex mode when a packet
is transmitted.
Table 13 summarizes the conditions for assertion of carrier sense, data loopback, and collision
signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
5.6.5
Error Signals
When the LXT972A Transceiver is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
When the MAC asserts TX_ER, the LXT972A Transceiver drives “H” symbols out on the TPOP/N
pins.
5.6.6
Collision
The LXT972A Transceiver asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time. Table 13
summarizes the conditions for assertion of carrier sense, data loopback, and collision signals.
Table 13. Carrier Sense, Loopback, and Collision Conditions
Speed
Duplex Condition
Carrier Sense
Test
Loop-
back1, 2
Operational
Loop-
back1, 2
Collision
100
Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex
Transmit or Receive
No
Transmit and Receive
10
Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex,
Register bit 16.8 = 0
Transmit or Receive
Yes
Transmit and Receive
Half-Duplex,
Register bit 16.8 = 1
Transmit or Receive
No
Transmit and Receive
1. Test Loopback is enabled when Register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see Section 5.6.7, “Loopback” on page 42.
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