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| 型号： | WJLXT972ALC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 38/97页 |
| 文件大小： | 1281K |
| 代理商： | WJLXT972ALC.A4 |
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Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Datasheet
43
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.6.7.2
Internal Digital Loopback (Test Loopback)
A test loopback function is provided for diagnostic testing of the LXT972A Transceiver. During
test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is
internally looped back by the LXT972A Transceiver and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by
setting the following register bits:
Register bit 0.14 = 1 (Setting to enable loopback mode)
Register bit 0.8 = 1 (Setting for full-duplex mode)
Register bit 0.12 = 0. (Disable auto-negotiation.)
5.7
100 Mbps Operation
5.7.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT972A Transceiver transmits and receives 5-bit symbols
across the network link.
Figure 12 shows the structure of a standard frame packet in 100BASE-X mode. When the MAC is
not actively transmitting data, the LXT972A Transceiver sends out Idle symbols on the line.
As Figure 12 shows, the MAC starts each transmission with a preamble pattern. As soon as the
LXT972A Transceiver detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT972A Transceiver transmits the End-of-Stream Delimiter (ESD,
symbols T and R) and then returns to transmitting Idle symbols.
For details on the symbols used, see 4B/5B coding listed in Table 14, “4B/5B Coding” on page 48.
Figure 12. 100BASE-X Frame Format
P0
P1
P6
SFD
64-Bit Preamble
(8 Octets)
Start-of-Frame
Delimiter (SFD)
DA
SA
Destination and Source
Address (6 Octets each)
L1
L2
Packet Length
(2 Octets)
D0
D1
Dn
Data Field
(Pad to minimum packet size)
Frame Check Field
(4 Octets)
CRC
I0
InterFrame Gap / Idle Code
(> 12 Octets)
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
IFG
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
B3466-01
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| WJLXT972MLCA4 | 制造商:Cortina Systems Inc 功能描述: |
| WJM1000 | 功能描述:射频模块 902-928 MHz US ISM EPC Class 1 Gen 2 RoHS:否 制造商:Linx Technologies 产品:Transceiver Modules 频带:902 MHz to 928 MHz 输出功率:- 15.5 dBm to + 12.5 dBm 接口类型:UART 工作电源电压:- 0.3 VDC to + 5.5 VDC 传输供电电流:38.1 mA 接收供电电流:22.7 mA 天线连接器类型:U.FL 最大工作温度:+ 85 C 尺寸:1.15 mm x 0.63 mm x 0.131 mm |
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