参数资料
型号: WJLXT972ALC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 54/97页
文件大小: 1281K
代理商: WJLXT972ALC.A4
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
58
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.10.4
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. Table 16 lists the four BSR modes of operation.
5.10.5
Device ID Register
Table 17 lists the bits for the Device ID register. For the current version of the JEDEC continuation
characters, see the specification update for the LXT972A Transceiver.
Table 16. BSR Mode of Operation
Mode
Description
1Capture
2Shift
3
Update
4
System Function
Table 17. Device ID Register for Intel
LXT972A Transceiver
Bits 31:28
Bits 27:12
Bits 11:8
Bits 7:1
Bit 0
Version
Part ID (Hex)
JEDEC Continuation Characters
JEDEC ID
1
Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The Intel JEDEC ID is FE
(1111 1110), which becomes 111 1110.
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