- 您现在的位置：买卖IC网 > PDF目录68583 > WJLXT972ALC.A4 (INTEL CORP) DATACOM, ETHERNET TRANSCEIVER, PQFP64 PDF资料下载
参数资料
| 型号： | WJLXT972ALC.A4 |
| 厂商： | INTEL CORP |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 27/97页 |
| 文件大小： | 1281K |
| 代理商： | WJLXT972ALC.A4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Datasheet
33
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.4.1
MDIO Control Mode and Hardware Control Mode
In the MDIO Control mode, the LXT972A Transceiver reads the Hardware Control Interface pins
to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control
reverts to the MDIO interface.
The following modes are available using either Hardware Control or MDIO control:
Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
Allow auto-negotiation/parallel-detection
In the Hardware Control Mode, the LXT972A Transceiver disables direct-write operations to the
MDIO registers through the MDIO Interface. On power-up or hardware reset, the LXT972A
Transceiver reads the Hardware Control Interface pins and sets the MDIO registers accordingly.
When the network link is forced to a specific configuration, the LXT972A Transceiver
immediately begins operating the network interface as commanded. When auto-negotiation is
enabled, the LXT972A Transceiver begins the auto-negotiation/parallel-detection operation.
5.4.2
Reduced-Power Modes
This section discusses the LXT972A Transceiver reduced-power modes.
5.4.2.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
The LXT972A Transceiver network port and clock are shut down.
All outputs are tristated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
5.4.2.2
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register. (See
Table 41 on page 79.) During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT972ALC.A4 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972MLC.A4-864101 | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
| WJLXT972MLC.A4-864115 | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
| WJLXT972MLC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
| WJLXT972MLC.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WJLXT972MLC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
| WJLXT972MLC.A4 S L7U9 | 制造商:Intel 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| WJLXT972MLC.A4-864115 | 功能描述:TXRX ETH 10/100 SGL PORT 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
| WJLXT972MLCA4 | 制造商:Cortina Systems Inc 功能描述: |
| WJM1000 | 功能描述:射频模块 902-928 MHz US ISM EPC Class 1 Gen 2 RoHS:否 制造商:Linx Technologies 产品:Transceiver Modules 频带:902 MHz to 928 MHz 输出功率:- 15.5 dBm to + 12.5 dBm 接口类型:UART 工作电源电压:- 0.3 VDC to + 5.5 VDC 传输供电电流:38.1 mA 接收供电电流:22.7 mA 天线连接器类型:U.FL 最大工作温度:+ 85 C 尺寸:1.15 mm x 0.63 mm x 0.131 mm |
发布紧急采购，3分钟左右您将得到回复。