参数资料
型号: WJLXT972ALC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 30/97页
文件大小: 1281K
代理商: WJLXT972ALC.A4
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
36
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.5
Establishing Link
Figure 7 shows an overview of link establishment for the LXT972A Transceiver.
Note:
When a link is established by parallel detection, the LXT972A Transceiver sets the duplex mode to
half-duplex, as defined by the IEEE 802.3 standard.
5.5.1
Auto-Negotiation
If not configured for forced operation, the LXT972A Transceiver attempts to auto-negotiate with
its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses
spaced 62.5
μs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data
pulses) may be absent or present to indicate a ‘0’ or a ‘1’. Each FLP burst exchanges 16 bits of
data, which are referred to as a “link code word”. All devices that support auto-negotiation must
implement the “Base Page” defined by the IEEE 802.3 standard (Registers 4 and 5).
The LXT972A Transceiver also supports the optional “Next Page” function as listed in Table 48,
5.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT972A Transceiver and its link partner communicate their
capabilities to each other. Both sides must receive at least three consecutive identical base pages for
negotiation to continue. Each side identifies the highest common capabilities that both sides
support, and each side configures itself accordingly.
Figure 7. Intel
LXT972A Transceiver Link Establishment Overview
Check Value
0.12
Start
Done
Enable
Auto-Neg/Parallel Detection
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 10T
Link Pulses
Listen for 100TX
Idle Symbols
Link Up?
NO
YES
Power-Up, Reset,
or Link Failure
Disable
Auto-Negotiation
0.12 = 0
0.12 = 1
B3496-01
相关PDF资料
PDF描述
WJLXT972ALC.A4 DATACOM, ETHERNET TRANSCEIVER, PQFP64
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