参数资料
型号: WJLXT972ALC.A4
厂商: INTEL CORP
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: ROHS COMPLIANT, LQFP-64
文件页数: 50/97页
文件大小: 1281K
代理商: WJLXT972ALC.A4
Intel
LXT972A Single-Port 10/100 Mbps PHY Transceiver
54
Datasheet
Document Number: 249186-004
Revision Date: 25-Oct-2005
5.9
Monitoring Operations
5.9.1
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
Register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed.
Register bits 1.2 and 17.10 are set to ‘1’ once the link is established.
Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and
duplex).
Note:
When the LXT972A Transceiver detects incorrect polarity for a 10BASE-T operation, Register bit
17.5 is set to ‘1’.
5.9.2
Monitoring Next Page Exchange
The LXT972A Transceiver offers an Alternate Next Page mode to simplify the next page exchange
process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next
Page mode is enabled, Register bit 6.1 is automatically cleared whenever a new negotiation process
takes place. This action prevents the user from reading an old value in bit 6.1 and assuming that
Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT972A
Transceiver uses Register bit 6.5 to indicate when the current received page is the base page. This
information is useful for recognizing when next pages must be resent due to a new negotiation
process starting. Register bits 6.1 and 6.5 are cleared when read.
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