参数资料
| 型号： | XRT83L34IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 54/99页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | XRT83L34IV-F-ND |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
55
the XRT83L34 device). In this case, the Microprocessor should continue to hold the "Write Strobe" (WR*/
R/W*) input pin "LOW" until it detects the "RDY*/DTACK*" output pin toggling "HIGH".
8. After waiting the appropriate amount of time for the data (on the Bi-Directional Data Bus) to stabilize and
can be safely accepted by the Microprocessor Interface block circuitry (within the XRT83L34 device); the
XRT83L34 device will indicate that this data can be latched into the "target" address location by toggling
the RDY*/DTACK* output pin "LOW".
9. After the Microprocessor detects the RDY*/DTACK* signal (from the XRT83L34 device) toggling "LOW", it
can then terminate the WRITE cycle by toggling the WR*/R/W* (Write Strobe) input pin "HIGH".
NOTE: Once the user toggles the "WR*/R/W* (Write Strobe) input pin "HIGH", then the Microprocessor Interface (of the
XRT83L34 device) will latch the contents of the Bi-Directional Data Bus (D[7:0]) into the "target" address location o
of the chip.
Figure _ presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during
an Intel-Asynchronous Mode Write Operation.
OPERATING THE MICROPROCESSOR INTERFACE IN THE MOTOROLA-ASYNCHRONOUS MODE
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table _.
FIGURE 26. ILLUSTRATION OF AN INTEL-ASYNCHRONOUS MODE WRITE OPERATION
ALE/AS
RD*/DS*
A[6:0]
CS*
D[7:0]
RDY/DTACK*
Data to be Written
Address of Target Register
WR*/R/W*
Microprocessor places “target”
Address value on A[6:0]
Address Decoding
Circuitry asserts
CS*
RDY* toggles “low” to indicate that
Valid data can be latched into “target”
Address location of chip
Write Operation begins
Here
RDY* toggles “high”
after Completion
Of Write Operation
Write Operation is
Terminated Here
Microprocessor Interface latches contents on
A[6:0] upon falling edge of ALE
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| XRT83SH314IB-F | IC LIU T1/E1/J1 14CH 304TBGA |
| XRT83SH38IB-F | IC LIU SH T1/E1/J1 8CH 225BGA |
| XRT86L30IV-F | IC LIU/FRAMER TI/E1/J1 SGL 128LQ |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83L34IVTR | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L34IVTR-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38ES | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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