参数资料
| 型号： | XRT83L34IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 6/99页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | XRT83L34IV-F-ND |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
11
TNEG_0/
CODES_0
TNEG_1/
CODES_1
TNEG_2/
CODES_2
TNEG_3/
CODES_3
3
126
105
100
I
Transmitter Negative-Polarity Data Input/Line Code Select Input:
The exact function of this input pin depends upon the following.
Whether the XRT83L34 device has been configured to operate in
the Single-Rail or Dual Mode
Whether the XRT83L34 device has been configure to operate in the
HOST or Hardware Mode, as described below
Dual-Rail Mode Operation - Transmit Negative-Polarity Data Input -
TNEG_n:
For Dual-Rail Applications, the System-Side Terminal Equipment should apply
the "negative-polarity" portion of the outbound DS1/E1 data-stream to this
input pin. Likewise, the System-Side Terminal Equipment should also apply
the "positive-polarity" portion of the outbound DS1/E1 data-stream to the
TPOS_n input pin.
The Transmit Section of Channel n will sample this input pin (along with
TPOS_n) upon the "user-selected" edge of TCLK_n. The Transmit Section of
Channel n will generate a "negative-polarity" pulse (via the outbound DS1/E1
line signal) anytime it samples this input pin at a logic "HIGH" level. The
Transmit Section of Channel n will NOT generate a "negative-polarity" pulse
(via the outbound DS1/E1 line signal) anytime it samples this input pin at a
logic LOW" level.
Single-Rail Mode Operation - Line Code Select Input/NO FUNCTION:
If the XRT83L34 device has been configured to operate in the Single-Rail
Mode, then the exact function of this input pin depends upon whether the chip
has been configured to operate in the HOST or Hardware Mode, as described
below.
HOST Mode Operation - NO FUNCTION:
If the XRT83L34 device has been configured to operate in both the HOST
Mode, and Single-Rail Modes, then this input pin has no function. Since this
input pin has an internal pull-down resistor, the user can either leave this pin
floating, or he/she can tie this pin to GND.
Hardware Mode Operation - Line Code Select Input pin - CODES_n:
If the XRT83L34 device has been configured to operate in both the Hardware
and Single-Rail Modes, then this input pin permits the user to configure a
given channel to enable or disable the HDB3/B8ZS Encoder and Decoder
blocks as described below.
If the user enables the HDB3/B8ZS Encoder and Decoder blocks then the
Channel will support the HDB3 line code (for E1 applications) and the B8ZS
line code (for T1 applications).
If the user disables the HDB3/B8ZS Encoder and Decoder blocks, then the
Channel will support the AMI line code (for either T1 and E1 applications).
LOW - Enables the HDB3/B8ZS Encoder and Decoder blocks within Channel
n.
HIGH - Disables the HDB3/B8ZS Encoder and Decoder blocks within Channel
n.
NOTE: Internally pulled “Low” with a 50k
resistor for channel _n
SIGNAL NAME
PIN #TYPE
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83L34IVTR | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L34IVTR-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38ES | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
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