- 您现在的位置：买卖IC网 > PDF目录300164 > ZL30402/QCG1 (ZARLINK SEMICONDUCTOR INC) ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 PDF资料下载
参数资料
| 型号： | ZL30402/QCG1 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件页数： | 15/44页 |
| 文件大小： | 472K |
| 代理商： | ZL30402/QCG1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
ZL30402
Data Sheet
22
Zarlink Semiconductor Inc.
Address: 01 H
Address: 04 H
Bit
Name
Functional Description
7RSV
Reserved.
6RSV
Reserved.
5LOCK
Lock. This bit goes high when the Core PLL is locked to the selected Acquisition
PLL.
4
HOLDOVER
Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection
of reference failure and subsequent transition from Normal to Holdover state takes
approximately: 0.750
s for 19.44 MHz reference, 0.850 s for 2.048 MHz
reference, 1.1
s for 1.544 MHz reference and 130 s for 8 kHz reference.
3RSV
Reserved.
2FLIM
Frequency Limit. This bit goes high when the Core PLL is pulled by the input
reference signal to the edge of its frequency tracking range set at ±104 ppm. This
bit may change state momentarily in the event of large jitter or wander excursions
occurring when the input reference is close to the frequency limit range.
1RSV
Reserved.
0RSV
Reserved.
Table 6 - Status Register 1 (R)
Bit
Name
Functional Description
Default
7
E3DS3/OC3
E3, DS3 or OC-3 clock select. Setting this bit to zero enables the
C155P/N outputs (pin 30 and pin 31) and enables the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high sets the C155 clock
outputs into high impedance and enables the C34/C44 output to
provide a C34 or C44 clock.
0
6E3/DS3
E3 or DS3 clock select. When E3DS3/OC3 bit is set high, a logic
low on the E3/DS3 bit selects a 44.736 MHz clock on the C34/C44
output and logic high selects a 34.368 MHz clock. When the
E3DS3/OC3 bit is set low, a logic low on the E3/DS3 bit selects an
11.184 MHz clock on the C34/C44 output and a logic high selects
an 8.592 MHz clock.
0
5-0
RSV
Reserved.
000000
Table 7 - Control Register 2 (R/W)
相关PDF资料 |
PDF描述 |
|---|---|
| ZL50112GAG2 | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50112GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50114GAG2 | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50114GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50232GD | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL30406 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406_06 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGC | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK MLTPLR SGL UP TO 19.44MHZ 64TQFP - Trays |
| ZL30406QGC1 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGG1 | 制造商:Microsemi Corporation 功能描述:IC PB FREE T1/E1 SYS. SYNC+STRATUM 3 H/O 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH CLOCK MULTIPLIER PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP |
发布紧急采购，3分钟左右您将得到回复。