- 您现在的位置：买卖IC网 > PDF目录300164 > ZL30402/QCG1 (ZARLINK SEMICONDUCTOR INC) ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 PDF资料下载
参数资料
| 型号： | ZL30402/QCG1 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80 |
| 文件页数： | 17/44页 |
| 文件大小： | 472K |
| 代理商： | ZL30402/QCG1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
ZL30402
Data Sheet
24
Zarlink Semiconductor Inc.
Address: 11 H
Address: 13 H
Bit
Name
Functional Description
Default
7RSV
Reserved.
0
6RSV
Reserved.
0
5-3
C1.5POA2
to
C1.5POA0
C1.5 Phase Offset Adjustment. These three bits allow for changing of
the phase offset of the C1.5o clock relative to the active input reference.
The phase offset is an unsigned number in a range from 0 to 7. Each
increment by one represents phase-offset advancement by 80.96 ns.
Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing
of 001 delays this clock by 80.96 ns from its present position
000
2-0
RSV
Reserved.
000
Table 11 - Control Register 3 (R/W)
Bit
Name
Functional Description
Default
7RSV
Reserved.
0
6RSV
Reserved.
0
5
C16dis
16.384 MHz Clock Disable. When set high, this bit tristates the 16.384 MHz clock
output.
0
4C8dis
8.192 MHz Clock Disable. When set high, this bit tristates the 8.192 MHz clock
output.
0
3C4dis
4.096 MHz Clock Disable. When set high, this bit tristates the 4.096 MHz clock
output.
0
2C2dis
2.048 MHz Clock Disable. When set high, this bit tristates the 2.048 MHz clock
output.
0
1
C1.5dis
1.544 MHz Clock Disable. When set high, this bit tristates the 1.544 MHz clock
output.
0
0RSV
Reserved.
0
Table 12 - Clock Disable Register 1 (R/W)
相关PDF资料 |
PDF描述 |
|---|---|
| ZL50112GAG2 | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50112GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50114GAG2 | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50114GAG | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| ZL50232GD | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL30406 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406_06 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGC | 制造商:Zarlink Semiconductor Inc 功能描述:PLL CLOCK MLTPLR SGL UP TO 19.44MHZ 64TQFP - Trays |
| ZL30406QGC1 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| ZL30406QGG1 | 制造商:Microsemi Corporation 功能描述:IC PB FREE T1/E1 SYS. SYNC+STRATUM 3 H/O 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH CLOCK MULTIPLIER PLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP 制造商:Microsemi Corporation 功能描述:IC PLL SONET/SDH CLK MULT 64TQFP |
发布紧急采购，3分钟左右您将得到回复。