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参数资料
| 型号： | ZL50408GDG2 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208 |
| 文件页数： | 115/144页 |
| 文件大小： | 1779K |
| 代理商： | ZL50408GDG2 |
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ZL50408
Data Sheet
72
Zarlink Semiconductor Inc.
CMD_STATUS_REG
Width
Access
Address
CPU interface command status
This register is not applicable in SSI+MII, MII-only and Remote/No
CPU interface modes.
8-bit
R/W
4
Default:
00
Bit #
Name
Type
Description
[0]
RXBUF_DONE
W
Set Control Frame Receive buffer ready, after CPU writes a
complete frame into the buffer. This bit is self-cleared.
RXBUF_RDY
R
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command
0 – CPU has to wait until this bit is 1 to write a new control
command
[1]
TXBUF1_DONE
W
Set Control Frame Transmit buffer1 ready, after CPU reads out a
complete frame from the buffer. This bit is self-cleared.
TXBUF1_RDY
R
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control
command
[2]
TXBUF2_DONE
W
Set Control Frame Transmit buffer2 ready, after CPU reads out a
complete frame from the buffer. This bit is self-cleared.
TXBUF2_RDY
R
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control
command
[3]
TXFIFO_RXDONE
W
Set this bit to indicate CPU received a whole frame (transmit FIFO
frame receive done), and flushed the rest of frame fragment, If
occurs. This bit will be self-cleared.
TXFIFO_RDY
R
Transmit FIFO has data for CPU to read
[4]
RXFIFO_EOF
W
Set this bit to indicate that the following Write to the Receive FIFO
is the last one. This bit will be self-cleared.
RXFIFO_SPOK
R
Receive FIFO has space for incoming CPU frame
[5]
RXFIFO_REALIGN
W
Set this bit to re-start the data that is sent from the CPU to Receive
FIFO (re-align). This feature can be used for software debug. For
normal operation must be '0'.
TXFIFO_EOF
R
Transmit FIFO End Of Frame
[7:6]
RSVD
R/W
Reserved
Register Table 5 - 4, CMD_STATUS_REG
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50409 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL50410 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
| ZL50410GDC208 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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