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参数资料
| 型号： | ZL50408GDG2 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208 |
| 文件页数： | 77/144页 |
| 文件大小： | 1779K |
| 代理商： | ZL50408GDG2 |
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ZL50408
Data Sheet
38
Zarlink Semiconductor Inc.
4.0
Data Forwarding Protocol
4.1
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is
responsible for multiplexing the data and the address. On a port’s “turn”, the RxDMA will move 8 bytes (or up to the
end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide
whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the
destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct
per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this
result into the per-port-per-class queue. Unicast TxQ’s are linked lists of transmission jobs, represented by their
associated frames’ FCB’s. There is one linked list for each transmission class for each port. There are 2
transmission classes for each of the 8 RMAC ports, and 4 classes for the GMAC and CPU ports – a total of 24
unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling
algorithm.
The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port’s turn, the
TxDMA will move 8 bytes (or up to the EOF) from memory into the port’s associated TxFIFO. After reading the EOF,
the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release
requests.
The frame is transmitted from the TxFIFO to the line.
4.2
Multicast Data Frame Forwarding
The search engine will resolve the destination ports of the multicast frame. This will be all ports within the VLAN (L2
multicast), or the ports contained in the portmap of the learned multicast MAC address or IP multicast group. After
receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can
be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped.
In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast
packet’s destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not
released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast
queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames).
There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the GMAC and CPU
ports. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for
the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50409 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL50410 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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