参数资料
型号: ZL50408GDG2
厂商: CONEXANT SYSTEMS
元件分类: 网络接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数: 37/144页
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
131
Zarlink Semiconductor Inc.
13.4.3
Typical CPU Timing Diagram for a CPU Read Cycle
Figure 16 - Typical CPU Timing Diagram for a CPU Read Cycle
Table 15 - CPU Read Timing
Description
(SCLK=100 Mhz)
(SCLK=50 Mhz)
Refer to Figure 16
Read Cycle
Symbol
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
Read Set up Time
TRS
10
P_A and P_CS# to falling
edge of P_RD#
Read Active Time
TRA
20
40
At least 2 SCLK cycles
Read Hold Time
TRH
2
P_A and P_CS# to rising
edge of P_RD#
Read Recovery time
TRR
30
60
At least 3 SCLK cycles
Data Valid time
TDV
12
P_DATA to falling edge of
P_RD#
Data Invalid time
TDI
10
P_DATA to rising edge of
P_RD#
P_CS#
P_RD#
P_DATA
(toCPU)
P_A[2:0]
T
RR
Recov ery Time
Inv alidtim e
ADD R0
T
RS
T
DV
T
RA
Activ eTim e
Valid tim e
DATA1
DATA0
T
DI
ADD R1
T
RH
T
RS
T
RA
Activ eTim e
T
RH
T
DI
T
DV
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