参数资料
型号: ZL50408GDG2
厂商: CONEXANT SYSTEMS
元件分类: 网络接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数: 6/144页
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
103
Zarlink Semiconductor Inc.
12.3.6.28
USER_PORT[7:0]_[LOW/HIGH] – User Define Logical Port 0~7
IC Address: h092+n(Low); CPU Address: h0570+2n(Low) (n = logical port number)
IC Address: h09A+n(High); CPU Address: h0571+2n(High)
Accessed by CPU and IC (R/W)
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
12.3.6.29
USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
IC Address: h0A2; CPU Address: h0590
Accessed by CPU and IC (R/W)
The chip allows the CPU to define the priority
12.3.6.30
USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
IC Address: h0A3; CPU Address: h0591
Accessed by CPU and IC (R/W)
Bit [6]:
Enable Well Known Port 6 Force Discard
Bit [7]:
Enable Well Known Port 7 Force Discard
70
TCP/UDP Logic Port Low
70
TCP/UDP Logic Port High
Bits [3:0]:
Priority setting, transmission + dropping, for logic port 0
Bit[0]
0 – Drop Precedence Level 0 (Lowest) (Default)
1 – Drop Precedence Level 1 (Highest)
Bits[3:1] Transmit Priority Level 0 (Lowest)
Transmit Priority Level 1
...
Transmit Priority Level 6
Transmit Priority Level 7 (Highest)
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 1 (Default 00)
Bits [3:0]:
Priority setting, transmission + dropping, for logic port 2
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 3 (Default 00)
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