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参数资料
型号： ZL50408GDG2
厂商： CONEXANT SYSTEMS
元件分类： 网络接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数： 74/144页
文件大小： 1779K
代理商： ZL50408GDG2
ZL50408
Data Sheet
35
Zarlink Semiconductor Inc.
Follow the standard Ethernet transmission format. CPU will see transmit enable (TXEN) be asserted by
ZL50408 and CPU can start receiving data. CPU will stop receiving data once TXEN is de-asserted by
ZL50408.
In summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the CPU is a simple
process that uses one direct access register only. In serial mode with MII interface, the CPU will be allowed to
transmit and receive frames using standard IEEE 802.3 Ethernet transmission format.
The details of sending an Ethernet Frame via the CPU interface is described in the Processor Interface Application
Note, ZLAN-26.
3.1.3
Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50408 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, and aging, etc. All Control frames are up to 40 bytes long.
Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that the
register accessed is the “Control frame data” register (address 111).
Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50408:
Memory read request
Memory write request
Learn Unicast MAC address
Delete Unicast MAC address
Search Unicast MAC address
Learn IP Multicast address
Delete IP Multicast address
Search IP Multicast address
Learn Multicast MAC address
Delete Multicast MAC address
Search Multicast MAC address
Note: Memory read and write requests by the CPU may include all internal memories which include statistic
counters, MAC address control link table and the 2 Mbit (256 KB) memory block.
In addition, the following types of Control frames are generated by the ZL50408 and sent to the CPU:
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn Unicast MAC address
Delete Unicast MAC address
Delete Multicast MAC address
Delete IP Multicast address
Response to search Unicast MAC address request from CPU
Response to search IP Multicast address request from CPU
Response to search Multicast MAC address request from CPU
The format of the Control Frame is described in the Processor Interface application note, ZLAN-26.
3.2
I2C Interface
The IC interface serves the function of configuring the ZL50408 at boot time. The master is the ZL50408, and the
slave is the EEPROM memory.
The IC interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
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ZL50409 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch
ZL50409GDC 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch
ZL50409GDC1 制造商:Microsemi Corporation 功能描述:
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ZL50410GDC208 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch
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