参数资料
型号: ZL50408GDG2
厂商: CONEXANT SYSTEMS
元件分类: 网络接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数: 12/144页
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
109
Zarlink Semiconductor Inc.
12.3.7.7
MIIC3 – MII Command Register 3
CPU Address: h0606
Accessed by CPU (R/W)
Note
: Writing to this register will initiate a serial management cycle to the MII management interface.
12.3.7.8
MIID0 – MII Data Register 0
CPU Address: h0607
Accessed by CPU (RO)
12.3.7.9
MIID1 – MII Data Register 1
CPU Address: h0608
Accessed by CPU (RO)
12.3.7.10
USD – One Micro Second Divider
CPU Address: h0609
Accessed by CPU (R/W)
Bits [4:0]
PHY_AD – 5-bit PHY address
Bit [5]
Reserved
Bit [6]
VALID – Data valid from PHY (Read Only)
Bit [7]
RDY – MII management interface ready (Read Only)
Bits [7:0]:
MII Data [7:0]
Bits [7:0]:
MII Data [15:8]
Bits [5:0]:
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50 MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20 MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1 usec for internal reference.
Bits [7:6]:
Reserved
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