参数资料
型号: ZL50408GDG2
厂商: CONEXANT SYSTEMS
元件分类: 网络接口
英文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装: 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数: 36/144页
文件大小: 1779K
代理商: ZL50408GDG2
ZL50408
Data Sheet
130
Zarlink Semiconductor Inc.
13.4.2
Typical CPU Timing Diagram for a CPU Write Cycle
Figure 15 - Typical CPU Timing Diagram for a CPU Write Cycle
Table 14 - CPU Write Timing
Description
(SCLK=100 Mhz)
(SCLK=50 Mhz)
Refer to Figure 15
Write Cycle
Symbol
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
Write Set up Time
TWS
10
P_A and P_CS# to falling
edge of P_WE#
Write Active Time
TWA
20
40
At least 2 SCLK cycles
Write Hold Time
TWH
2
P_A and P_CS# to rising
edge of P_WE#
Write Recovery time
TWR
30
60
At least 3 SCLK cycles
Data Set Up time
TDS
10
P_DATA to falling edge of
P_WE#
Data Hold time
TDH
2
P_DATA to rising edge of
P_WE#
P_CS#
P_W E#
P_DATA
(to dev ice)
P_A[2:0]
T
WR
Recov ery Time
Holdtim e
ADD R0
T
WS
T
WA
Activ eTim e
Set up time
DATA1
DATA0
ADDR 1
T
WH
T
WS
T
WA
Activ eTim e
T
WH
T
DH
T
DH
T
DS
T
DS
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