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参数资料
型号： ZL50408GDG2
厂商： CONEXANT SYSTEMS
元件分类： 网络接口
英文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA208
封装： 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208
文件页数： 79/144页
文件大小： 1779K
代理商： ZL50408GDG2
ZL50408
Data Sheet
4
Zarlink Semiconductor Inc.
Changes Summary
July 2003
Initial Release
November 2003
Clarified IP Multicast support is up to 4K groups, as it wasn’t mentioned in the data sheets
Updated Ball Signal Description Table (1.3, “Ball Signal Descriptions“ on page 14):
clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs OR outputs
clarified that M9_MTXCLK is an input only
Updated 1.4, “Signal Mapping and Internal pull-up/Down Configuration“ on page 20 to indicate operation of
the internal pull-up/down resistors in different modes
Clarified 10.1.3, “GMAC Reference Clock (GREF_CLK) Speed Requirement“ on page 53 on usage of
GREF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
I2C address mapping was corrected for QOSCn registers
Added Maximum Junction Temperature to 13.1, “Absolute Maximum Ratings“ on page 127
Updated I/O voltage levels to use TTL spec values rather than % of Vcc (13.2, “DC Electrical
Characteristics“ on page 127)
February 2004
Added the following to the Feature List:
4 K jumbo frames
IEEE 802.3ad support
Reverse MII/GPSI
Added section on PHY addresses (2.2.4, “PHY Addresses“ on page 28)
Clarified that they are hard-coded
Fixed error in DS on sending Ethernet Frames via 8/16-bit or serial interface.
The Status Bytes is sent before the frame, for both Tx and Rx
Added more cross-references to available AppNotes
Added section on Stacked VLAN (Q-in-Q) (5.9.3, “VLAN Stacking (Q-in-Q)“ on page 43) and IP Multicast
Switching (5.10, “IP Multicast Switching“ on page 44) since they weren’t really discussed in the DS
Added more clock descriptions to 10.0, “Clocks“ on page 53
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
August 2004
Added section Changes Summary to document
Added section on SCL clock generation (10.2.2, “SCL“ on page 54)
Interrupt Register was incorrectly identified as read only, should be read/write
Clarified that only bit [7] is not self-clearing
Updated CPU timing diagrams to clarify timing (13.4, “AC Characteristics and Timing“ on page 129)
November 2004
Added section 1.6, “Default Switch Configuration and Initialization Sequence“ on page 24
Updated CPU timing diagrams to clarify P_A timing (13.4, “AC Characteristics and Timing“ on page 129)
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