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参数资料
| 型号： | ZL50408GDG2 |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-192, LBGA-208 |
| 文件页数： | 95/144页 |
| 文件大小： | 1779K |
| 代理商： | ZL50408GDG2 |
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ZL50408
Data Sheet
54
Zarlink Semiconductor Inc.
10.2
Clock Generation
10.2.1
MDC
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50 MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
10.2.2
SCL
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal to
50kHz (M_CLK/1000). If a different speed clock other than 50 MHz is used on M_CLK, the USD register must be
programmed to reset SCL.
10.2.3
Ethernet Interface Clocks
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 100 M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode.
If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 10 M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed
accordingly.
For the CPU port in serial+MII mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for
100 M mode or M_CLK/20 for 10 M mode. M_CLK needs to be a 50 MHz clock in this mode.
The gigabit port generates an external TXCLK interface clock in GMII mode. It is equal to the 125 MHz GREF_CLK.
If the GMAC port is configured in Reverse MII mode, RXCLK is generated from GREF_CLK and is equal to
GREF_CLK/2 for 100 M mode (no support for 10M Reverse MII mode). GREF_CLK needs to be a 50 MHz clock in
this mode.
11.0
Hardware Statistics Counters
11.1
Hardware Statistics Counters List
ZL50408 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the
CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the filtering
counter (detected by queue manager). The following is the wrapped signal sent to the CPU through the command
block.
See Processor Interface application note, ZLAN-26, for more information.
11.2
IEEE 802.3 HUB Management (RFC 1516)
11.2.1
Event Counters
11.2.1.1
PortReadableFrames
Counts the number of frames of valid frame length that have been received on this port.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50409 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL50410 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
| ZL50410GDC208 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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