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| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 17/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
TABLE 13. POWER SUPPLY REQUIREMENTS
EXAMPLE
Now the output inductance can be calculated using
Equation 6, where V INM is the maximum input voltage:
V OUT × ? ? 1 ? OUT
? ?
PARAMETER
Input voltage (V IN )
Output voltage (V OUT )
Output current (I OUT )
RANGE
3.0V to 14.0V
0.6V to 5.0V
0A to ~25A
VALUE
12V
1.2V
20A
L OUT
=
? V
? V INM
f sw × I opp
?
?
(EQ. 6)
Output voltage ripple
(V orip )
Output load step (I ostep )
< 3% of V OUT
< Io
1% of V OUT
50% of I o
The average inductor current is equal to the maximum
output current. The peak inductor current (I Lpk ) is calculated
using Equation 7 where I OUT is the maximum output current.
Output load step rate
Output deviation due to loadstep
-
-
10A/μs
± 50mV
I Lpk = I OUT +
I opp
2
(EQ. 7)
Maximum PCB temp.
Desired efficiency
Other considerations
+120°C
-
Various
+85°C
85%
Optimize for
small size
Select an inductor rated for the average DC current with a
peak current rating above the peak current computed .
In overcurrent or short-circuit conditions, the inductor may
have currents greater than 2x the normal maximum rated
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor
core loss increases with frequency, so there is a trade-off
between a small output filter made possible by a higher
switching frequency and getting better power supply
output current. It is desirable to use an inductor that still
provides some inductance to protect the load and the
MOSFETs from damaging currents in this situation.
Once an inductor is selected, the DCR and core losses in
the inductor are calculated. Use the DCR specified in the
inductor manufacturer ’s datasheet.
efficiency. Size can be decreased by increasing the
switching frequency at the expense of efficiency. Cost can
P LDCR = DCR × I Lrms
2
(EQ. 8)
I Lrms = I OUT +
( I )
be minimized by using through-hole inductors and
capacitors; however these components are physically large.
To start the design, select a switching frequency based on
Table 14. This frequency is a starting point and may be
adjusted as the design progresses.
I Lrms is given by
2
opp
12
2
(EQ. 9)
TABLE 14. CIRCUIT DESIGN CONSIDERATIONS
where I OUT is the maximum output current. Next, calculate
FREQUENCY RANGE
200kHz to 400kHz
400kHz to 800kHz
800kHz to 1.4MHz
EFFICIENCY
Highest
Moderate
Lower
CIRCUIT SIZE
Larger
Smaller
Smallest
the core loss of the selected inductor. Since this calculation
is specific to each inductor and manufacturer, refer to the
chosen inductor datasheet. Add the core loss and the ESR
loss and compare the total loss to the maximum power
dissipation recommendation in the inductor datasheet.
OUTPUT CAPACITOR SELECTION
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (I opp ), which will reduce output capacitance and
produce a low output ripple voltage, but may also
compromise output transient load performance. Therefore, a
balance must be struck between output ripple and optimal
load transient performance. A good starting point is to select
the output inductor ripple equal to the expected load
transient step magnitude (I ostep ; see Equation 5):
Several trade-offs must also be considered when selecting
an output capacitor. Low ESR values are needed to have a
small output deviation during transient load steps (V osag ) and
low output voltage ripple (V orip ). However, capacitors with
low ESR, such as semi-stable (X5R and X7R) dielectric
ceramic capacitors, also have relatively low capacitance
values. Many designs can use a combination of high
capacitance devices and low ESR devices in parallel.
For high ripple currents, a low capacitance value can cause
a significant amount of output voltage ripple. Likewise, in
I OPP = I OSTEP
17
(EQ. 5)
high transient load steps, a relatively large amount of
capacitance is needed to minimize the output voltage
deviation while the inductor current ramps up or down to the
new steady state output current value.
FN6876.3
August 29, 2012
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| ZL6105ALAF | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
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