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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 26/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
If the user has configured the device to restart, the device
will wait the preset delay period (if configured to do so) and
will then check the device temperature. If the temperature
has dropped below a threshold that is approximately +15°C
lower than the selected temperature fault limit, the device
will attempt to re-start. If the temperature still exceeds the
fault limit the device will wait the preset delay period and
retry again.
device using the DLY(0,1) pins, and the user may also
configure a specific ramp rate using the SS pin. Any device
that is configured for tracking mode will ignore its soft-start
delay and ramp time settings (SS and DLY(0,1) pins) and its
output will take on the turn-on/turn-off characteristics of the
reference voltage present at the VTRK pin. All of the
ENABLE pins in the tracking group must be connected
together and driven by a single logic source. Tracking is
configured via the I 2 C/SMBus interface by using the
TRACK_CONFIG PMBus command. Please refer to
Application Note AN2033 for more information on
configuring tracking mode using PMBus.
The default response from a temperature fault is an
immediate shutdown of the device. The device will
continuously check for the fault condition, and once the fault
V IN
has cleared the ZL6100 will be re-enabled.
Please refer to Application Note AN2033 for details on how
ZL6100
GH
SW
GL
Q1
Q2
L1
V OUT
C1
to select specific temperature fault response options via
I 2 C/SMBus.
Voltage Tracking
Numerous high performance systems place stringent
demands on the order in which the power supply voltages are
turned on. This is particularly true when powering FPGAs,
ASICs, and other advanced processor devices that require
multiple supply voltages to power a single die. In most cases,
the I/O interface operates at a higher voltage than the core
and therefore the core supply voltage must not exceed the I/O
supply voltage according to the manufacturers' specifications.
Voltage tracking protects these sensitive ICs by limiting the
differential voltage between multiple power supplies during
the power-up and power down sequence. The ZL6100
integrates a lossless tracking scheme that allows its output
to track a voltage that is applied to the VTRK pin with no
external components required. The VTRK pin is an analog
input that, when tracking mode is enabled, configures the
voltage applied to the VTRK pin to act as a reference for the
device’s output regulation.
The ZL6100 offers two modes of tracking:
1. Coincident . This mode configures the ZL6100 to ramp
its output voltage at the same rate as the voltage applied
to the VTRK pin.
2. Ratiometric . This mode configures the ZL6100 to ramp
its output voltage at a rate that is a percentage of the
voltage applied to the VTRK pin. The default setting is
50%, but an external resistor string may be used to
configure a different tracking ratio.
Figure 19 illustrates the typical connection and the two
tracking modes.
The master ZL6100 device in a tracking group is defined as
the device that has the highest target output voltage within
the group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode. A
delay of at least 10ms must be configured into the master
26
V TRK
V OUT
V TRK
V OUT
Time
COINCIDENT
V OUT
V TRK
V OUT
Time
RATIOMETRIC
FIGURE 19. TRACKING MODES
Voltage Margining
The ZL6100 offers a simple means to vary its output higher
or lower than its nominal voltage setting in order to
determine whether the load device is capable of operating
over its specified supply voltage range. The MGN command
is set by driving the MGN pin or through the I 2 C/SMBus
interface. The MGN pin is a tri-level input that is continuously
monitored and can be driven directly by a processor I/O pin
or other logic-level output.
The ZL6100’s output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output
will be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of V NOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I 2 C/SMBus interface to as high as V NOM + 10% or
FN6876.3
August 29, 2012
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相关代理商/技术参数 |
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| ZL6105 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital DC/DC Controller with Drivers and Auto |
| ZL6105ALAF | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ZL6105ALAF-01 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING - B - Trays |
| ZL6105ALAFT | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ZL6105ALAFTK | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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