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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 24/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
then:
The UVLO voltage can also be set to any value between
? D + f MIN
? 2 ( f SW ? f MIN ) ?
f SW (D) = ?
Otherwise:
f SW ( D ) = f PROG
? D NOM ?
(EQ. 36)
(EQ. 37)
2.85V and 16V via the I 2 C/SMBus interface.
Once an input undervoltage fault condition occurs, the
device can respond in a number of ways as shown in Steps
1. Continue operating without interruption.
Refer to Figure 17. Due to quantizing effects inside the IC,
the ZL6100 will decrease its frequency in steps between f SW
and f MIN . The quantity and magnitude of the steps will
depend on the difference between f SW and f MIN as well as
the frequency range.
It should be noted that adaptive frequency mode is not
available for current sharing groups and is not allowed when
the device is placed in auto-detect mode and a clock source
is present on the SYNC pin, or if the device is outputting a
clock signal on its SYNC pin.
Power Management Functional Description
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL6100
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The
UVLO threshold (V UVLO ) can be set between 2.85V and 16V
using the UVLO pin. The simplest implementation is to
connect the UVLO pin as shown in Table 20. If the UVLO pin
is left unconnected, the UVLO threshold will default to 4.5V.
TABLE 20. UVLO THRESHOLD SETTINGS
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device will remain in
shutdown until instructed to restart.
3. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
The default response from a UVLO fault is an immediate
shutdown of the device. The device will continuously check
for the presence of the fault condition. If the fault condition is
no longer present, the ZL6100 will be re-enabled.
Please refer to Application Note AN2033 for details on how
to configure the UVLO threshold or to select specific UVLO
fault response options via the I 2 C/SMBus interface.
Output Overvoltage Protection
The ZL6100 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry
from being subjected to a voltage higher than its prescribed
limits. A hardware comparator is used to compare the actual
output voltage (seen at the VSEN pin) to a threshold set to
15% higher than the target output voltage (the default
setting). If the VSEN voltage exceeds this threshold, the PG
PIN SETTING
LOW
OPEN
HIGH
UVLO THRESHOLD
(V)
3
4.5
10.8
pin will de-assert and the device can then respond in a
number of ways as shown in Steps 1 and 2.
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
2. Turn off the high-side MOSFET and turn on the low-side
I f the desired UVLO threshold is not one of the listed
choices, the user can configure a threshold between 2.85V
and 16V by connecting a resistor between the UVLO pin and
SGND by selecting the appropriate resistor from Table 21.
TABLE 21. UVLO RESISTOR VALUES
MOSFET. The low-side MOSFET remains ON until the
device attempts a restart.
The default response from an overvoltage fault is to
immediately shut down. The device will continuously check
for the presence of the fault condition, and when the fault
condition no longer exists the device will be re-enabled.
R UVLO
(k Ω )
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
UVLO
(V)
2.85
3.14
3.44
3.79
4.18
4.59
5.06
5.57
6.13
6.75
R UVLO
(k Ω )
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
UVLO
(V)
7.42
8.18
8.99
9.9
10.9
12
13.2
14.54
16
For continuous overvoltage protection when operating from
an external clock, the only allowed response is an immediate
shutdown.
Please refer to Application Note AN2033 for details on how
to select specific overvoltage fault response options via
I 2 C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output before
the power supply’s control IC is enabled. Certain
applications require that the converter not be allowed to sink
current during start up if a pre-bias condition exists at the
24
FN6876.3
August 29, 2012
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