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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 5/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
Electrical Specifications
V DD = 12V, T A = -40°C to +85°C, unless otherwise specified. Typical values are at T A = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
UVLO Set-point Accuracy
UVLO Hysteresis
Factory default
CONDITIONS
(Note 19)
-150
–
TYP
–
3
(Note 19)
150
–
UNIT
mV
%
UVLO Delay
Configurable via
I 2 C/SMBus
0
–
–
–
100
2.5
%
μs
Power-Good V OUT Threshold
Power-Good V OUT Hysteresis
Power-Good Delay
Factory default
Factory default
Using pin-strap or resistor (Note 15)
–
–
0
90
5
–
–
–
200
% V OUT
%
ms
Configurable via
I 2 C/SMBus
0
–
500
s
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
Factory default
Configurable via I 2 C/SMBus
Factory default
–
0
–
85
–
115
–
110
–
% V OUT
% V OUT
% V OUT
VSEN Undervoltage Hysteresis
Configurable via
I 2 C/SMBus
0
–
–
5
115
–
% V OUT
% V OUT
VSEN Undervoltage/Overvoltage Fault
Factory default
–
16
–
μs
Response Time
Current Limit Set-point Accuracy
Configurable via
I 2 C/SMBus
5
–
–
±10
60
–
μs
% FS
(V OUT Referenced)
(Note 16)
Current Limit Set-point Accuracy
–
±10
–
% FS
(Ground referenced)
(Note 16)
Current Limit Protection Delay
Factory default
–
5
–
t SW
(Note 17)
Configurable via I 2 C/SMBus
1
–
32
t SW
(Note 17)
Temperature Compensation of
Current Limit Protection Threshold
Thermal Protection Threshold
Factory default
Configurable via I 2 C/SMBus
Factory default
–
100
–
4400
–
125
–
12700
–
ppm/°C
ppm/°C
°C
(Junction Temperature)
Thermal Protection Hysteresis
Configurable via
I 2 C/SMBus
-40
–
–
15
125
–
°C
°C
NOTES:
9. Does not include margin limits.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. V OUT measured at the termination of the VSEN+ and VSEN- sense points.
12. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approx 2ms, where in normal mode it may vary up to 4ms.
13. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
14. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
15. Factory default Power-Good delay is set to the same value as the soft-start ramp time.
16. Percentage of Full Scale (FS) with temperature compensation applied.
17. t SW = 1/f SW , where f SW is the switching frequency.
18. Normal capacitance of logic pins is 5pF.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN6876.3
August 29, 2012
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