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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 9/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
Power Conversion Overview
>
Input Voltage Bus
PG
EN
MGN
ILIM(0,1)
SS
DLY(0,1)
V(0,1)
FC(0,1)
VDD
VR
VTRK
Power Management
NVM
BST
MOSFET
SYNC
GEN
Digital
Compensator
D-PWM
Drivers
SW
V OUT
NLR
SYNC
PLL
ADC
Σ
-
VSEN
ADC
+
ISEN B
ISENA
REFCN
DAC
D DC
VD D
VSEN+
I C
2
SALRT
SDA
SCL
Communication
ADC
M UX
Voltage
Sensor
TEMP
VSEN-
XTEMP
SA(0,1)
Sensor
FIGURE 3. ZL6100 BLOCK DIAGRAM
The ZL6100 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme that uses external
MOSFETs, capacitors, and an inductor to perform power
conversion.
V IN
During time D, QH is on and V IN – V OUT is applied across
the inductor. The current ramps up as shown in Figure 5.
When QH turns off (time 1-D), the current flowing in the
inductor must continue to flow from the ground up through QL,
during which the current ramps down. Since the output
capacitor C OUT exhibits a low impedance at the switching
VR
BST
DB
C IN
frequency, the AC component of the inductor current is filtered
from the output voltage so the load sees nearly a DC voltage.
GH
QH
ZL6100
SW
GL
CB
QL
V OUT
C OUT
V IN - V OUT
IL PK
FIGURE 4. SYNCHRONOUS BUCK CONVERTER
0
I O
Figure 4 illustrates the basic synchronous buck converter
topology showing the primary power train components. This
converter is also called a step-down converter, as the output
-V OUT
IL V
voltage must always be lower than the input voltage. In its
most simple configuration, the ZL6100 requires two external
D
TIME
1-D
N-channel power MOSFETs, one for the top control
MOSFET (QH) and one for the bottom synchronous
MOSFET (QL). The amount of time that QH is on as a
fraction of the total switching period is known as the duty
cycle D , which is described by Equation 1:
FIGURE 5. INDUCTOR WAVEFORM
Typically, buck converters specify a maximum duty cycle that
effectively limits the maximum output voltage that can be
realized for a given input voltage. This duty cycle limit
V OUT
D ≈ -------------
V IN
9
(EQ. 1)
ensures that the lowside MOSFET is allowed to turn on for a
minimum amount of time during each switching cycle, which
enables the bootstrap capacitor (CB in Figure 4) to be
charged up and provide adequate gate drive voltage for the
FN6876.3
August 29, 2012
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL6105 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital DC/DC Controller with Drivers and Auto |
| ZL6105ALAF | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ZL6105ALAF-01 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING - B - Trays |
| ZL6105ALAFT | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ZL6105ALAFTK | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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