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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 27/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页
ZL6100
as low as 0V, where V NOM is the nominal output voltage set
TABLE 23. SMBus ADDRESS VALUES
point determined by the V0 and V1 pins. A safety feature
prevents the user from configuring the output voltage to
exceed V NOM + 10% under any conditions.
The margin limits and the MGN command can both be set
individually through the I 2 C/SMBus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I 2 C interface.
Please refer to Application Note AN2033 for detailed
instructions on modifying the margining configurations.
I 2 C/SMBus Communications
The ZL6100 provides an I 2 C/SMBus digital interface that
enables the user to configure all aspects of the device
operation as well as monitor the input and output
parameters. The ZL6100 can be used with any standard 2-
wire I 2 C host device. In addition, the device is compatible
with SMBus version 2.0 and includes an SALRT line to help
R SA
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
SMBus
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
R SA
(k Ω )
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
SMBus
ADDRESS
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
mitigate bandwidth limitations related to continuous fault
monitoring. Pull-up resistors are required on the I 2 C/SMBus
as specified in the SMBus 2.0 specification. The ZL6100
accepts most standard PMBus commands. When controlling
the device with PMBus commands, it is recommended that
the enable pin is tied to SGND.
I 2 C/SMBus Device Address Selection
When communicating with multiple SMBus devices using the
I 2 C/SMBus interface, each device must have its own unique
address so the host can distinguish between the devices.
The device address can be set according to the pin-strap
options listed in Table 22. Address values are right-justified.
TABLE 22. SMBus DEVICE ADDRESS SELECTION
SA0
If more than 25 unique device addresses are required or if
other SMBus address values are desired, both the SA0 and
SA1 pins can be configured with a resistor to SGND
according to Equation 38 and Table 24.
SMBusaddress = 25 ? ( SA1 index ) + ( SA0 index ) ( in decimal )
(EQ. 38)
Using this method, the user can theoretically configure up to
625 unique SMBus addresses, however the SMBus is
inherently limited to 128 devices so attempting to configure
an address higher than 128 (0x80) will cause the device
address to repeat (i.e, attempting to configure a device
address of 129 (0x81) would result in a device address of 1).
Therefore, the user should use index values 0-4 on the SA1
pin and the full range of index values on the SA0 pin, which
LOW
OPEN
HIGH
will provide 125 device address combinations.
LOW
0x20
0x21
0x22
Note that the SMBus address 0x4B is reserved for device
SA1
OPEN
HIGH
0x23
0x26
0x24
0x27
0x25
Reserved
test and cannot be used in the system.
TABLE 24. SMBus ADDRESS INDEX VALUES
If additional device addresses are required, a resistor can be
connected to the SA0 pin according to Table 23 to provide
up to 25 unique device addresses. In this case, the SA1 pin
should be tied to SGND.
R SA
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
SA0 or SA1
INDEX
0
1
2
3
4
5
6
7
8
9
10
11
R SA
(k Ω )
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
SA0 or SA1
INDEX
13
14
15
16
17
18
19
20
21
22
23
24
27
31.6
12
FN6876.3
August 29, 2012
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