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| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 23/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
Non-linear Response (NLR) Settings
The ZL6100 incorporates a non-linear response (NLR) loop
that decreases the response time and the output voltage
deviation in the event of a sudden output load current step. The
NLR loop incorporates a secondary error signal processing
path that bypasses the primary error loop when the output
begins to transition outside of the standard regulation limits.
This scheme results in a higher equivalent loop bandwidth than
what is possible using a traditional linear loop.
When a load current step function imposed on the output
causes the output voltage to drop below the lower regulation
limit, the NLR circuitry will force a positive correction signal
that will turn on the upper MOSFET and quickly force the
output to increase. Conversely, a negative load step (i.e.
removing a large load current) will cause the NLR circuitry to
force a negative correction signal that will turn on the lower
MOSFET and quickly force the output to decrease.
The ZL6100 has been pre-configured with appropriate NLR
settings that correspond to the loop compensation settings in
Table 19. Please refer to Application Note AN2032 for more
details regarding NLR settings.
Efficiency Optimized Driver Dead-time Control
The ZL6100 utilizes a closed loop algorithm to optimize the
dead-time applied between the gate drive signals for the top
and bottom FETs. In a synchronous buck converter, the
MOSFET drive circuitry must be designed such that the top
and bottom MOSFETs are never in the conducting state at
the same time. Potentially damaging currents flow in the
circuit if both top and bottom MOSFETs are simultaneously
on for periods of time exceeding a few nanoseconds.
Conversely, long periods of time in which both MOSFETs are
off reduce overall circuit efficiency by allowing current to flow
in their parasitic body diodes.
It is therefore advantageous to minimize this dead-time to
provide optimum circuit efficiency. In the first order model of
a buck converter, the duty cycle is determined by
Equation 34:
Adaptive Diode Emulation
Most power converters use synchronous rectification to
optimize efficiency over a wide range of input and output
conditions. However, at light loads the synchronous
MOSFET will typically sink current and introduce additional
energy losses associated with higher peak inductor currents,
resulting in reduced efficiency. Adaptive diode emulation
mode turns off the low-side FET gate drive at low load
currents to prevent the inductor current from going negative,
reducing the energy losses and increasing overall efficiency.
Diode emulation is available to single-phase devices.
Note: the overall bandwidth of the device may be reduced
when in diode emulation mode. It is recommended that diode
emulation is disabled prior to applying significant load steps.
Adaptive Frequency Control
Since switching losses contribute to the efficiency of the
power converter, reducing the switching frequency will
reduce the switching losses and increase efficiency. The
ZL6100 includes Adaptive Frequency Control mode, which
effectively reduces the observed switching frequency as the
load decreases.
Adaptive frequency mode is enabled by setting bit 0 of
MISC_CONFIG to 1 and is only available while the device is
operating within Adaptive Diode Emulation Mode. As the
load current is decreased, diode emulation mode decreases
the GL on-time to prevent negative inductor current from
flowing. As the load is decreased further, the GH pulse width
will begin to decrease while maintaining the programmed
frequency, f PROG (set by the FREQ_SWITCH command).
f SW (D)
f PROG
f MIN
V OUT
D ≈ (EQ. 34)
V IN
However, non-idealities exist that cause the real duty cycle to
0
D NOM
2
DUTY CYCLE
DUTY CYCLE
D
extend beyond the ideal. Dead-time is one of those
non-idealities that can be manipulated to improve efficiency.
The ZL6100 has an internal algorithm that constantly adjusts
dead-time non-overlap to minimize duty cycle, thus maximizing
efficiency. This circuit will null out dead-time differences due to
component variation, temperature, and loading effects.
FIGURE 17. ADAPTIVE FREQUENCY
Once the GH pulse width (D) reaches 50% of the nominal
duty cycle, D NOM (determined by V IN and V OUT ), the
switching frequency will start to decrease according to
Equations 35, 36 and 37:
This algorithm is independent of application circuit parameters
such as MOSFET type, gate driver delays, rise and fall times
and circuit layout. In addition, it does not require drive or
MOSFET voltage or current waveform measurements.
23
If:
D <
D NOM
2
(EQ. 35)
FN6876.3
August 29, 2012
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相关代理商/技术参数 |
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| ZL6105 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital DC/DC Controller with Drivers and Auto |
| ZL6105ALAF | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ZL6105ALAF-01 | 制造商:Intersil Corporation 功能描述:ADAPTIVE DIGITAL DC-DC CONTROLLER W/ DRIVERS & I-SHARING - B - Trays |
| ZL6105ALAFT | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ZL6105ALAFTK | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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