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参数资料
| 型号： | ZL6100EVAL2Z |
| 厂商： | Intersil |
| 文件页数： | 22/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2CH USB ZL6100 |
| 标准包装： | 1 |
| 系列： | * |
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ZL6100
Loop Compensation
The ZL6100 operates as a voltage-mode synchronous buck
Step 1: Using Equation 32, calculate the resonant frequency
of the LC filter, fn .
controller with a fixed frequency PWM scheme. Although the
ZL6100 uses a digital control loop, it operates much like a
traditional analog PWM controller. Figure 16 is a simplified
f n =
1
2 π L × C
(EQ. 32)
block diagram of the ZL6100 control loop, which differs from
an analog control loop only by the constants in the PWM and
compensation blocks. As in the analog controller case, the
compensation block compares the output voltage to the
Step 2: Based on Table 19 determine the FC0 settings.
Step 3: Calculate the ESR zero frequency (f ZESR ) using
Equation 33.
desired voltage reference and compensation zeroes are
added to keep the loop stable. The resulting integrated error
signal is used to drive the PWM logic, converting the error
f zesr =
1
2 π CRc
(EQ. 33)
signal to a duty cycle to drive the external MOSFETs.
V IN
Step 4: Based on Table 19 determine the FC1 setting.
Adaptive Compensation
DPWM
D
1-D
L
C
R O
V OUT
Loop compensation can be a time-consuming process,
forcing the designer to accommodate design trade-offs
related to performance and stability across a wide range of
operating conditions. The ZL6100 offers an adaptive
compensation mode that enables the user to increase the
R C
Compensation
FIGURE 16. CONTROL LOOP BLOCK DIAGRAM
In the ZL6100, the compensation zeros are set by configuring
the FC0 and FC1 pins or via the I 2 C/SMBus interface once
the user has calculated the required settings. This method
eliminates the inaccuracies due to the component tolerances
stability over a wider range of loading conditions by
automatically adapting the loop compensation coefficients
for changes in load current.
Setting the loop compensation coefficients through the
I 2 C/SMBus interface allows for a second set of coefficients
to be stored in the device in order to utilize adaptive loop
compensation. This algorithm uses the two sets of
compensation coefficients to determine optimal
compensation settings as the output load changes. Please
refer to Application Note AN2033 for further details on
PMBus commands.
associated with using external resistors and capacitors
required with traditional analog controllers. Utilizing the loop
compensation settings shown in Table 19 will yield a
conservative crossover frequency at a fixed fraction of the
switching frequency (f SW /20) and 60° of phase margin.
TABLE 19. PIN-STRAP SETTINGS FOR LOOP COMPENSATION
FC0 RANGE
f sw /60 < f n < f sw /30
f sw /120 < f n < f sw /60
f sw /240 < f n < f sw /120
FC0 PIN
HIGH
OPEN
LOW
FC1 RANGE
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
Reserved
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
Reserved
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
FC1 PIN
HIGH
OPEN
LOW
HIGH
OPEN
LOW
HIGH
OPEN
22
Reserved
LOW
FN6876.3
August 29, 2012
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