参数资料
型号: AD9882KSTZ-100
厂商: Analog Devices Inc
文件页数: 11/40页
文件大小: 0K
描述: IC INTERFACE/DVI 100MHZ 100LQFP
标准包装: 1
应用: 视频
接口: 模拟,DVI
电源电压: 3.15 V ~ 3.45 V
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 管件
安装类型: 表面贴装
AD9882A
Rev. 0 | Page 19 of 40
THEORY OF OPERATION: DIGITAL INTERFACE
Table 11. Digital Interface Pin List
Pin Type
Mnemonic
Function
Value
Pin
Number
RX0+
Digital input Channel 0 true
33
Digital Video Data
Inputs
RX0–
Digital input Channel 0 complement
32
RX1+
Digital input Channel 1 true
36
RX1–
Digital input Channel 1 complement
35
RX2+
Digital input Channel 2 true
39
RX2–
Digital input Channel 2 Complement
38
RXC+
Digital data clock true
41
Digital Video Clock
Inputs
RXC–
Digital data clock complement
42
Termination Control
RTERM
Control pin for setting the internal termination
resistance
28
Outputs
DE
Data enable
3.3 V CMOS
86
HSOUT
Hsync output
3.3 V CMOS
88
VSOUT
Vsync output
3.3 V CMOS
87
CTL0, CTL1, CTL2, CTL3
Decoded control bit outputs
3.3 V CMOS
22–25
HDCP
DDCSCL
HDCP slave serial port data clock
3.3 V CMOS
53
DDCSDA
HDCP slave serial port data I/O
3.3 V CMOS
54
MCL
HDCP master serial port data clock
3.3 V CMOS
81
MDA
HDCP master serial port data I/O
3.3 V CMOS
82
Power Supply
VD
Main power supply
3.15 V to 3.45 V
PVD
PLL power Supply
3.15 V to 3.45 V
VDD
Output power supply
2.2 V to 3.6 V
GND
Ground supply
0 V
DIGITAL INTERFACE PIN DESCRIPTIONS
Digital Data Inputs
RX0+ Positive Differential Input Data (Channel 0)
RX0– Negative Differential Input Data (Channel 0)
RX1+ Positive Differential Input Data (Channel 1)
RX1– Negative Differential Input Data (Channel 1)
RX2+ Positive Differential Input Data (Channel 2)
RX2– Negative Differential Input Data (Channel 2)
These six pins receive three pairs of differential, low voltage
swing input pixel data from a DVI transmitter.
Digital Clock Inputs
RXC+ Positive Differential Input Clock
RXC– Negative Differential Input Clock
These two pins receive the differential, low voltage swing input
pixel clock from a DVI transmitter.
Termination Control
RTERM—Internal Termination Set Pin
This pin is used to set the termination resistance for all of the
digital interface high speed inputs. To set, place a resistor of
value equal to 10× the desired input termination resistance
between this pin (Pin 28) and ground supply. Typically, the
value of this resistor should be 500 .
Outputs
DE—Data Enable Output
This pin outputs the state of data enable (DE). The AD9882A
decodes DE from the incoming stream of data. The DE signal is
high during active video and is low while there is no active
video.
DDCSCL—HDCP Slave Serial Port Data Clock
Used for communicating with the HDCP-enabled DVI
transmitter.
DDCSDA—HDCP Slave Serial Port I/O
For use in communicating with the HDCP-enabled DVI
transmitter.
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