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| 型号： | AD9882KSTZ-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/40页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE/DVI 100MHZ 100LQFP |
| 标准包装： | 1 |
| 应用： | 视频 |
| 接口： | 模拟，DVI |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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AD9882A
Rev. 0 | Page 29 of 40
Table 23. Active Vsync Override Settings
Override
Result
0
Autodetermines the active Vsync
1
Override; Bit 0 determines the
active Vsync.
The default for this register is 0.
0x10 0
Active Vsync Select
This bit is used to select the active Vsync when the override bit
is set (Bit 1).
Table 24. Active Vsync Select Settings
Select
Result
0
Vsync input
1
Sync separator output
The default for this register is 0.
0x11 7
Clamp Function
This bit enables/disables clamping.
Table 25. Clamp Input Signal Source Settings
Clamp Function
Function
0
Internally generated clamp enabled
1
Clamping disabled
0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the trailing edge of Hsync.
1 disables clamping. The three channels are clamped when the
clamp signal is active.
Power-up default value for clamp function is 0.
0x11 6
Red Clamp Select
A bit that determines whether the red channel is clamped to
ground or to midscale. For RGB video, all three channels are
referenced to ground. For YPbPr, the Y channel is referenced to
ground, but the PbPr channels are referenced to midscale.
Clamping to midscale clamps to Pin 74.
Table 26. Red Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 5
Green Clamp Select
This bit determines whether the green channel is clamped to
ground or to midscale.
Table 27. Green Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 4
Blue Clamp Select
This bit determines whether the blue channel is clamped to
ground or to midscale.
Table 28. Blue Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 74)
The default setting for this register is 0.
0x11 3
Coast Select
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin
or the output from the sync separator needs to be made
(Register 0x10, Bits 1, 0). To disable coast, the user must set
Register 0x11, Bit 2 to 1 and Register 0x11, Bit 1 to 1.
Table 29. Coast Enable Settings
Select
Result
0
Coast disabled
1
Internally generated coast signal
The default for this register is 1.
0x11 2
Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into the PLL.
When disabling coast, Register 11, Bit 2 must be set to 1 and
Register 0x11, Bit 1 must be set to 1. This register works only
when coast is disabled. It does not work with internal coast.
Table 30. Coast Input Polarity Override Settings
Override Bit
Result
0
Coast polarity determined by chip
1
Coast polarity determined by user
The default for coast polarity override is 0.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9883 | 制造商:AD 制造商全称:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 制造商:AD 制造商全称:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
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