参数资料
型号: AD9882KSTZ-100
厂商: Analog Devices Inc
文件页数: 25/40页
文件大小: 0K
描述: IC INTERFACE/DVI 100MHZ 100LQFP
标准包装: 1
应用: 视频
接口: 模拟,DVI
电源电压: 3.15 V ~ 3.45 V
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 管件
安装类型: 表面贴装
AD9882A
Rev. 0 | Page 31 of 40
0x14 0
4:2:2 Output Mode Select
This bit configures the output data in 4:2:2 mode. This mode
can be used to reduce the number of data lines used from 24 to
16 for applications using YPbPr graphics signals. A timing
diagram for this mode is shown in Figure 17. Recommended
input and output configurations are shown in Table 39. In
4:2:2 mode, the red and blue channels can be interchanged to
help satisfy board layout or timing requirements, but the green
channel must be configured for Y.
Table 38. 4:2:2 Output Mode Select
Select
Output Mode
0
4:4:4
1
4:2:2
Table 39. 4:2:2 Input/Output Configuration
Channel
Input Connection
Output Format
Red
Pr
Pb/Pr
Green
Y
Blue
Pr
High impedance
0x15 7
Hsync Detect
This bit is used to indicate when activity is detected on the
HSYNC input pin (Pin 79). If Hsync is held high or low, activity
is not detected.
Table 40. Hsync Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 20 shows where this function is implemented.
0x15 6
Sync-on-Green Detect
This bit is used to indicate when sync activity is detected on the
sync-on-green input pin (Pin 64).
Table 41. Sync-on-Green Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 20 shows where this function is implemented.
Note that if no sync signal is presented on the green video
input, normal video might still trigger activity.
0x15 5
Vsync Detect
This bit is used to indicate when activity is detected on the
Vsync input pin (Pin 80). If Vsync is held high or low, activity is
not detected.
Table 42. Vsync Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 20 shows where this function is implemented.
0x15 4
Digital Interface Clock Detect
This bit is used to indicate when activity is detected on the
digital interface clock input.
Table 43. Digital Interface Clock Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 20 shows where this function is implemented.
0x15 3
Active Interface
This bit is used to indicate which interface should be active,
analog or digital. It checks for activity on the analog interface
and for activity on the digital interface, then determines which
should be active according to Table 44. Specifically, analog
interface detection is determined by OR’ing Bits 7, 6, and 5 in
this register. Digital interface detection is determined by Bit 4 in
this register. If both interfaces are detected, the user can
determine which has priority via Bit 1 in Register 0x0F. The
user can override this function via Bit 2 in Register 0x0F. If the
override bit is set to Logic 1, then this bit will be forced to the
same state as Bit 1 in Register 0x0F.
Table 44. Active Interface Results
Bits 7, 6, or 5
(Analog
Detection)
Bit 4
(Digital
Detection)
Override
AI
0
Soft power-
down (seek
mode)
0
1
0
1
0
1
0
Bit 1 in 0x0F
X
1
Bit 1 in 0x0F
AI = 0 means analog interface. AI = 1 means digital interface.
The override bit is in Register 0x0F, Bit 2.
0x16 7
AHS Active Hsync
This bit indicates which Hsync input source is being used by
the PLL (Hsync input or sync-on-green). Bits 6 and 7 in
Register 0x15 determine which source is used. If both Hsync
and SOG are detected, the user can determine which has
priority via Bit 3 in Register 0x10. The user can override this
function via Bit 4 in Register 0x10. If the override bit is set to
Logic 1, then this bit will be forced to the same state as Bit 3 in
Register 0x10.
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