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| 型号： | AD9887AKSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/52页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 32 of 52
2-WIRE SERIAL REGISTER MAP
The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write
and read the control registers through the 2-line serial interface port.
Table 9. Control Register Map
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Description
0x00
RO
7:0
Chip Revision
Bit 7 through Bit 4 represent functional revisions to the analog
interface. Bit 3 through Bit 0 represent nonfunctional related
revisions. Revision 0 = 0000 0000.
0x01
R/W
7:0
01101001
PLL Divide Ratio
MSBs
This register is for Bits[11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first when
0x02
R/W
7:4
1101****
PLL Divide Ratio
LSBs
This register is for Bits[3:0] of the PLL divider. Links to the PLL divide
0x03
R/W
7:2
1*******
Clock Generator
Controls
Bit 7—Must be set to 1 for proper device operation.
*01*****
Bits[6:5]—VCO Range Select. Selects VCO frequency range (see the
PLL section).
***001**
Bits[4:2]—Charge-Pump Current. Varies the current that drives the
low-pass filter (see the PLL section).
0x04
R/W
7:3
10000***
Clock Phase Adjust
Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32)
0x05
R/W
7:0
10000000
Clamp Placement
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
0x06
R/W
7:0
10000000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
0x07
R/W
7:0
00100000
Hsync Output
Pulse Width
Sets the number of pixel clocks that HSOUT remains active.
0x08
R/W
7:0
10000000
REDGAIN
Controls ADC input range (contrast) of red channel. Bigger values
result in less contrast.
0x09
R/W
7:0
10000000
GREENGAIN
Controls ADC input range (contrast) of green channel. Bigger values
result in less contrast.
0x0A
R/W
7:0
10000000
BLUEGAIN
Controls ADC input range (contrast) of blue channel. Bigger values
result in less contrast.
0x0B
R/W
7:1
1000000*
REDOFST
Controls dc offset (brightness) of red channel. Bigger values decrease
brightness.
0x0C
R/W
7:1
1000000*
GREENOFST
Controls dc offset (brightness) of green channel. Bigger values
decrease brightness.
0x0D
R/W
7:1
1000000*
BLUEOFST
Controls dc offset (brightness) of blue channel. Bigger values decrease
brightness.
0x0E
R/W
7:3
1*******
Mode Control 1
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. Logic 0 = single-channel mode; Logic 1 = dual-channel mode.
*1******
Bit 6—Output Mode. Determines interleaved or parallel output mode.
Logic 0 = interleaved mode; Logic 1 = parallel mode.
**0*****
Bit 5—Output Port Phase (OUTPHASE). Determines which port outputs
the first data byte after Hsync. Logic 0 = B port; Logic 1 = A port.
***0****
Bit 4—HSYNC Output Polarity. Logic 0 = logic high sync; Logic 1 =
logic low sync.
****0***
Bit 3—VSYNC Output Invert. Logic 0 = invert; Logic 1 = no invert.
0x0F
R/W
7:0
1*******
PLL and Clamp
Control
Bit 7—HSYNC Input Polarity. Indicates the polarity of incoming HSYNC
signal to the PLL. Logic 0 = active low; Logic 1 = active high.
*1******
Bit 6—COAST Input Polarity. Changes polarity of external coast signal.
Logic 0 = active low; Logic 1 = active high.
**0*****
Bit 5—Clamp Input Signal Source (EXTCLMP). Chooses between HSYNC
for CLAMP signal and another external signal to be used for clamping.
Logic 0 = HSYNC; Logic 1 = externally provided clamp signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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