AD9887A
Rev. B | Page 37 of 52
0x0C 7:1
Green Channel Offset Adjust (GREENOFST)
A 7-bit offset binary word that sets the dc offset of the
green channel. See REDOFST (0B).
0x0D 7:1
Blue Channel Offset Adjust (BLUEOFST)
A 7-bit offset binary word that sets the dc offset of the
blue channel. See REDOFST (0B).
Mode Control 1
0x0E 7
Channel Mode
A bit that determines whether all pixels are presented to
a single port (Port A), or if alternating pixels are demulti-
plexed to Port A and Port B.
Table 12. Channel Mode Settings
DEMUX
Function
0
All data goes to Port A
1
Alternate pixels go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high imped-
ance state. The maximum data rate for single-port mode
is 100 MHz. The timing diagrams show the effects of
this option.
The power-up default value is 1.
0x0E 6
Output Mode
A bit that determines whether all pixels are
simultaneously presented to Port A and Port B upon
every second DATACK rising edge or alternately
presented to Port A and Port B upon successive
DATACK rising edges.
Table 13. Output Mode Settings
PARALLEL
Function
0
Data is interleaved
1
Data is simultaneous upon every other data clock
When in single-port mode (DEMUX = 0), this bit is
option.
The power-up default value is PARALLEL = 1.
0x0E 5
Output Port Phase
One bit that determines whether even or odd pixels go to
Port A.
Table 14. Output Port Phase (OUTPHASE) Settings
OUTPHASE
First Pixel After Hsync
1
Port B
0
Port A
In normal operation (OUTPHASE = 0) when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented to Port A,
every subsequent odd sample goes to Port A, and all
even samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
When DEMUX = 0, this bit is ignored because data
always comes out of only Port A.
0x0E 4
HSYNC Output Polarity
One bit that determines the polarity of the HSYNC
output and the SOG output.
Table 15 shows the effect of
this option. SYNC indicates the logic state of the sync
pulse.
Table 15. HSYNC Output Polarity Settings
Setting
HSYNC
0
Logic 1 (negative polarity)
1
Logic 0 (positive polarity)
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
0x0E 3
VSYNC Output Invert
One bit that inverts the polarity of the VSYNC output.
Table 16 shows the effect of this option.
Table 16. VSYNC Output Polarity Settings
Setting
VSYNC Output
0
Invert
1
No invert
The default setting for this register is 1. This option
works on both the analog and digital interfaces.