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参数资料
| 型号： | AD9887AKSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/52页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 39 of 52
0x0F 1
Green Clamp Select
A bit that determines whether the green channel is
clamped to ground or to midscale.
Table 23. Green Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 109)
The default setting for this register is 0.
0x0F 0
Blue Clamp Select
A bit that determines whether the blue channel is
clamped to ground or to midscale.
Table 24. Blue Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 99)
The default setting for this register is 0.
Mode Control 2
0x10 7
Data Output Clock Invert (CKINV)
A control bit for the inversion of the output data clocks
(Pin 134 and Pin 135). This function only works for the
digital interface. When not inverted, data is output upon
the trailing edge of the data clock. See Figure 37 through
Figure 40 for how this affects timing.
Table 25. Data Output Clock Invert (CKINV) Settings
CKINV
Function
0
Not inverted
1
Inverted
The default for this register is 0.
0x10 6
Pixel Select
This bit selects either one or two pixels per clock mode
for the digital interface. It determines whether the
output is from a single port (even port only) at the full
data rate, or from two ports (both even and odd ports) at
half the full data rate per port. Logic 0 selects one pixel
per clock (even port only). Logic 1 selects two pixels per
clock (both ports). See the Digital Interface Timing
representations of this function. Note that this function
operates exactly like the demux function on the analog
interface.
Table 26. Pixel Select Settings
Pixel Select
Function
0
One pixel per clock
1
Two pixels per clock
The default for this register is 0.
0x10 5, 4
Output Drive
These two bits select the drive strength for the high
speed digital outputs (all data output and clock output
pins). Higher drive strength results in faster rise/fall
times and enables easier capture of data in general.
Lower drive strength results in slower rise/fall times and
reduces EMI and digitally generated power supply noise.
The exact timing specifications for each of these modes
are specified in Table 7.
Table 27. Output Drive Strength Settings
Bit 5
Bit 4
Result
1
X
High drive strength
0
1
Medium drive strength
0
Low drive strength
The default for this register is 11. This option works on
both the analog and digital interfaces.
0x10 3
Power-Down Outputs (PDO)
This bit can put the outputs into a high impedance mode.
This applies to all outputs except SOGOUT and REFOUT.
Table 28. Power-Down Output (PDO) Settings
PDO
Function
0
Normal operation
1
Three-state
The default for this register is 0. This option works on
both the analog and digital interfaces.
0x10 2
Sync Detect Polarity
This pin controls the polarity of the sync detect output
pin (Pin 136).
Table 29. Sync Detect Polarity Settings
Polarity
Function
0
Activity = Logic 1 output
1
Activity = Logic 0 output
The default for this register is 0. This option works on
both the analog and digital interfaces.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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