AD9887A
Rev. B | Page 33 of 52
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Description
***1****
Bit 4—Clamp Input Signal Polarity (name also same as Bit 6). Valid only
with external CLAMP signal. Logic 0 = active low; Logic 1 = active high.
****0***
Bit 3—External Clock Select (EXTCLK). Shuts down the PLL and allows
the use of an external clock to drive the part. Logic 0 = uses internal
PLL; Logic 1 = bypasses the internal PLL.
*****0**
Bit 2—Red Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 120 and 118)
******0*
Bit 1—Green Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 111 and 109)
*******0
Bit 0—Blue Clamp Select. Logic 0 selects clamp to ground; Logic 1
selects clamp to midscale. (Voltage at Pin 101 and 99)
0x10
R/W
7:2
0*******
Mode Control 2
Bit 7—CKINV: Data Output Clock Invert. Logic 0 = not inverted;
Logic 1 = inverted (digital interface only).
*0******
Bit 6—Pixel Select. Selects either one or two pixels per clock mode.
Logic 0 = one pixel/clock; Logic 1 = two pixels/clock (digital interface
only).
**11****
Bit 5, 4—Output Drive. Selects among high, medium, and low output
drive strength. Logic 11 or Logic 10 = high, Logic 01 = medium, and
Logic 00 = low.
****0***
Bit 3—PDO: High Impedance Outputs. Logic 0 = normal; Logic 1 =
high impedance.
*****1**
Bit 2—Sync Detect Polarity. This bit sets the polarity for the SCDT pin.
Logic 1 = active high; Logic 0 = active low.
0x11
RO
7:1
1*******
Sync Detection
and Active
Interface Control
Bit 7—Analog Interface HSYNC Detect. It is set to Logic 1 if Hsync is
present on the analog interface; otherwise, it is set to Logic 0.
*1******
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1 if
sync is present on the green video input; otherwise, it is set to 0.
**1*****
Bit 5—Analog Interface VSYNC Detect. It is set to Logic 1 if Vsync is
present on the analog interface; otherwise, it is set to Logic 0.
***1****
Bit 4—Digital Interface Clock Detect. It is set to Logic 1 if the clock is
present on the digital interface; otherwise, it is set to Logic 0.
****1***
Bit 3—Active Interface (AI). This bit indicates which interface is active.
Logic 0 = analog interface; Logic 1 = digital interface.
*****1**
Bit 2—Active Hsync (AHS). This bit indicates which analog Hsync is being
used. Logic 0 = HSYNC input pin; Logic 1 = Hsync from sync-on-green.
******1*
Bit 1—Active Vsync (AVS). This bit indicates which analog Vsync is being
used. Logic 0 = VSYNC input pin; Logic 1 = Vsync from sync-on-green.
0x12
R/W
7:0
0*******
Active Interface
Bit 7—Active Interface Override (AIO). If set to Logic 1, the user can
select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 0x11.
*0******
Bit 6—Active Interface Select (AIS). Logic 0 selects the analog interface
as active. Logic 1 selects the digital interface as active. Note that the
indicated interface is active only if Bit 7 is set to Logic 1 or if both
interfaces are active (Bit 6 or Bit 7 and Bit 4 = Logic 1 in Register 0x11).
**0*****
Bit 5—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 4. If set to Logic 0, the active interface is
selected via Bit 2 in Register 0x11.
***0****
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects sync-on-green as the active sync. Note that the indicated
Hsync is used only if Bit 5 is set to Logic 1 or if both syncs are active
(Bit 6 and Bit 7 = Logic 1 in Register 0x11).
****0***
Bit 3—Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 2. If set to Logic 0, the active interface is
selected via Bit 1 in Register 0x11.