AD9887A
Rev. B | Page 41 of 52
0x11 1
Active VSYNC (AVS)
This bit determines which VSYNC to use for the analog
interface, the VSYNC input or the sync separator output.
If both VSYNC and composite SOG are detected, VSYNC
is selected. The user can override this function via Bit 3
in Register 0x12. If the override bit is set to Logic 1, this
bit is forced to the set state of Bit 2 in Register 0x12.
Table 36. Active VSYNC Results
Bit 5 (VSYNC Detect)
0
1
0
1
X
1
Bit 2 in Register 0x12
1 The override bit is Bit 3 in Register 0x12.
2 AVS = 0 means VSYNC input.
3 AVS = 1 means sync separator.
0x12 7
Active Interface Override (AIO)
Set this bit (Bit 3 in Register 0x11) to Logic 1 to override
the automatic interface selection. When overriding the
automatic interface selection, the active interface is set
via Bit 6 in this register.
Table 37. Active Interface Override Settings
AIO
Result
0
Autodetermines the active interface
1
Override, Bit 6 determines the active interface
The default for this register is 0.
12
6
Active Interface Select (AIS)
This bit is used under two conditions. It is used to select
the active interface when the override bit (Bit 7) is set.
Alternately, it is used to determine the active interface
when the override bit is not set, but both interfaces are
detected.
Table 38. Active Interface Select Settings
AIS
Result
0
Analog interface
1
Digital interface
The default for this register is 0.
0x12 5
Active HSYNC Override
This bit is used to override the automatic HSYNC selection
(Bit 2 in Register 0x11). To initiate, set this bit to Logic 1.
When overriding the automatic HSYNC selection, the
active HSYNC is set via Bit 4 in this register.
Table 39. Active HSYNC Override Settings
Override
Result
0
Autodetermines the active interface
1
Override, Bit 4 determines the active interface
The default for this register is 0.
0x12 4
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit (Bit 5) is set.
Alternately, it is used to determine the active Hsync
when the override bit is not set, but both Hsyncs are
detected.
Table 40. Active Hsync Select Settings
Select
Result
0
HSYNC input
1
Sync-on-green input
The default for this register is 0.
0x12 3
Active Vsync Override
This bit is used to override the automatic Vsync selection
(Bit 1 in Register 0x11). To initiate this, set this bit to
Logic 1. When overriding the automatic Vsync selection,
the active interface is set via Bit 2 in this register.
Table 41. Active VSYNC Override Settings
Override
Result
0
Autodetermines the active Vsync
1
Override, Bit 2 determines the active Vsync
The default for this register is 0.
0x12 2
Active Vsync Select
This bit is used to select the active Vsync when the
override bit (Bit 3) is set.
Table 42. Active VSYNC Select Settings
Select
Result
0
VSYNC input
1
Sync separator output
The default for this register is 0.
0x12 1
Coast Select
This bit is used to select which coast source is active, the
COAST input pin or Vsync. If Vsync is selected, users
must decide whether to use the VSYNC input pin or the
output from the sync separator (Bit 3 and Bit 2).
Table 43. Coast Select Settings
Select
Result
0
COAST input pin
1
Vsync (see above text)