- 您现在的位置：买卖IC网 > PDF目录1894 > AD9887AKSZ-140 (Analog Devices Inc)IC INTRFACE ANALOG/DVI 160-MQFP PDF资料下载
参数资料
| 型号： | AD9887AKSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/52页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
AD9887A
Rev. B | Page 38 of 52
0x0F 7
HSYNC Input Polarity
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL HSYNC input.
Table 17. HSYNC Input Polarity (HSPOL) Settings
HSPOL
Function
0
Active low
1
Active high
Active low is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which
is the falling edge. The rising edge has no effect.
Active high is inverted from the traditional Hsync, with
a positive-going pulse; therefore, timing is based on the
leading edge of Hsync, which is now the rising edge.
The device operates if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which might
generate clamping errors.
The power-up default value is HSPOL = 1.
0x0F 6
COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
Table 18. COAST Input Polarity (CSTPOL) Settings
CSTPOL
Function
0
Active low
1
Active high
Active low means that the clock generator ignores HSYNC
inputs when coast is low and continues operating at the
same nominal frequency until coast goes high.
Active high means that the clock generator ignores HSYNC
inputs when coast is high and continues operating at the
same nominal frequency until coast goes low.
This function must be used with the COAST polarity
override bit (Register 0x14, Bit 1).
The power-up default value is CSTPOL = 1.
0x0F 5
Clamp Input Signal Source
A bit that determines the source of clamp timing.
Table 19. Clamp Input Signal Source (EXTCLMP) Settings
EXTCLMP
Function
0
Internally generated clamp
1
Externally provided clamp signal
Logic 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and
duration is counted from the trailing edge of Hsync.
Logic 1 enables the external CLAMP input pin. The
three channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
0x0F 4
CLAMP Input Signal Polarity
A bit that determines the polarity of the externally
provided CLAMP signal.
Table 20. CLAMP Input Signal Polarity (EXTCLMP) Settings
EXTCLMP
Function
0
Active low
1
Active high
Logic 0 means that the circuit clamps when CLAMP is high
and passes the signal to the ADC when CLAMP is low.
Logic 1 means that the circuit clamps when CLAMP is low
and passes the signal to the ADC when CLAMP is high.
The power-up default value is CLAMPOL = 1.
0x0F 3
External Clock Select
A bit that determines the source of the pixel clock.
Table 21. External Clock Select (EXTCLK) Settings
EXTCLK
Function
0
Internally generated clock
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL divide ratio (PLLDIV) is ignored and the
clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
0x0F 2
Red Clamp Select
A bit that determines whether the red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr (or
YUV), the Y channel is referenced to ground, but the
CbCr channels are referenced to midscale. Clamping to
midscale actually clamps to Pin 118, RCLAMPV.
Table 22. Red Clamp Select Settings
Clamp
Function
0
Clamp to ground
1
Clamp to midscale (Pin 118)
The default setting for this register is 0.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9888KSZ-170 | IC ANALOG INTRFC 170MSPS 128MQFP |
| AD9895KBCZRL | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| AD9910BSVZ-REEL | IC DDS 1GSPS 14BIT PAR 100TQFP |
| AD9911BCPZ-REEL7 | IC DDS 500MSPS DAC 10BIT 56LFCSP |
| AD9912ABCPZ | IC DDS 1GSPS DAC 14BIT 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
发布紧急采购，3分钟左右您将得到回复。